Patents by Inventor Yukitoshi Hirose

Yukitoshi Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282246
    Abstract: Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative semiconductor device includes (i) a substrate having multiple conductive first contacts, (ii) a semiconductor die coupled to the substrate and having multiple conductive second contacts, and (iii) multiple wire bonds electrically coupling individual ones of the first contacts to corresponding ones of the second contacts. The first contacts, the second contacts, or both the first and second contacts can be arranged in a pair-staggered pattern. More specifically, the first contacts and/or the second contacts can extend sequentially along an axis of the semiconductor device, and adjacent pairs of the first contacts and/or adjacent pairs of the second contacts can be staggered relative to the axis.
    Type: Application
    Filed: February 17, 2023
    Publication date: September 7, 2023
    Inventors: Yukitoshi Hirose, Yushi Inoue
  • Patent number: 9449951
    Abstract: A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: September 20, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Yukitoshi Hirose, Yushi Inoue, Shiro Harashima, Takuya Moriya, Chihoko Yokobe
  • Patent number: 9159664
    Abstract: A semiconductor device may include, but is not limited to: a wiring hoard; and first and second chips stacked over the wiring board. The wiring board includes a plurality of first data terminals and a plurality of second data terminals. One of the first and second chips is sandwiched between the wiring board and the other of the first and second chips. The first chip includes a plurality of first data pads. The second chip includes a plurality of second data pads and a plurality of third data pads. The first data terminals of the wiring board are electrically connected respectively to the first data pads of the first chip and further respectively to the second data pads of the second chip. The second data terminals are electrically connected respectively to the third data pads of the second chip and electrically disconnected from the first chip.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: October 13, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Yushi Inoue, Yukitoshi Hirose
  • Publication number: 20150091170
    Abstract: A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Applicant: PS4 Luxco S.a,r.1.
    Inventors: Yukitoshi HIROSE, Yushi INOUE, Shiro HARASHIMA, Takuya MORIYA, Chihoko YOKOBE
  • Patent number: 8937392
    Abstract: A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: January 20, 2015
    Assignee: PS4Luxco S.a.r.l.
    Inventors: Yukitoshi Hirose, Yushi Inoue, Shiro Harashima, Takuya Moriya, Chihoko Yokobe
  • Patent number: 8861215
    Abstract: A device includes: a wiring board having first and second surfaces opposing each other; and a plurality of memory packages on the first surface. The wiring board includes: a first set of terminals on the first surface; a plurality of second sets of terminals on the first surface; and a plurality of first signal lines. The terminals of the first set receive respective ones of a plurality of first signals supplied from a control device. Each of the second sets is provided for a corresponding one of the memory packages. The terminals of each of the second sets contact the corresponding one of the memory packages. The first signal lines extend from respective ones of the terminals of the first set while coupling respective ones of the terminals of each of the second sets. The first signal lines extend on the first surface without extending in the wiring board.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: October 14, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Miho Nomoto, Yukitoshi Hirose
  • Patent number: 8680881
    Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: March 25, 2014
    Inventors: Yutaka Uematsu, Hideki Osaka, Satoshi Nakamura, Satoshi Muraoka, Mitsuaki Katagiri, Ken Iwakura, Yukitoshi Hirose
  • Publication number: 20120261837
    Abstract: A semiconductor device may include, but is not limited to: a wiring hoard; and first and second chips stacked over the wiring board. The wiring board includes a plurality of first data terminals and a plurality of second data terminals. One of the first and second chips is sandwiched between the wiring board and the other of the first and second chips. The first chip includes a plurality of first data pads. The second chip includes a plurality of second data pads and a plurality of third data pads. The first data terminals of the wiring board are electrically connected respectively to the first data pads of the first chip and further respectively to the second data pads of the second chip. The second data terminals are electrically connected respectively to the third data pads of the second chip and electrically disconnected from the first chip.
    Type: Application
    Filed: July 7, 2011
    Publication date: October 18, 2012
    Inventors: Yushi INOUE, Yukitoshi Hirose
  • Patent number: 8288852
    Abstract: In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: October 16, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Uematsu, Yukitoshi Hirose
  • Publication number: 20110317372
    Abstract: A device includes: a wiring board having first and second surfaces opposing each other; and a plurality of memory packages on the first surface. The wiring board includes: a first set of terminals on the first surface; a plurality of second sets of terminals on the first surface; and a plurality of first signal lines. The terminals of the first set receive respective ones of a plurality of first signals supplied from a control device. Each of the second sets is provided for a corresponding one of the memory packages. The terminals of each of the second sets contact the corresponding one of the memory packages. The first signal lines extend from respective ones of the terminals of the first set while coupling respective ones of the terminals of each of the second sets. The first signal lines extend on the first surface without extending in the wiring board.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 29, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Miho NOMOTO, Yukitoshi HIROSE
  • Publication number: 20110234249
    Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.
    Type: Application
    Filed: March 10, 2011
    Publication date: September 29, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yutaka UEMATSU, Hideki OSAKA, Satoshi NAKAMURA, Satoshi MURAOKA, Mitsuaki KATAGIRI, Ken IWAKURA, Yukitoshi HIROSE
  • Patent number: 7965572
    Abstract: A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: June 21, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Uematsu, Tatsuya Saito, Yoji Nishio, Yukitoshi Hirose
  • Patent number: 7880491
    Abstract: The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips includes a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device also includes a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: February 1, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Yukitoshi Hirose
  • Patent number: 7851898
    Abstract: Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: December 14, 2010
    Assignees: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Satoshi Nakamura, Takashi Suga, Mitsuaki Katagiri, Yukitoshi Hirose
  • Patent number: 7768312
    Abstract: A semiconductor device of the invention has a plurality of P-channel transistors, to which resistance elements are inserted in series, prepared on a pull-up side of a driver such that an ON resistance value on the P-channel transistor side and a resistance value of the resistance element can be selected. In addition, also on a pull-down side of the driver, a plurality of N-channel transistors to which resistance elements are inserted in series are prepared such that an ON resistance value on the N-channel transistor side and a resistance value of the resistance element can be selected. A driver section having a linear current-voltage characteristic is realized by combination of those described.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: August 3, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Yukitoshi Hirose
  • Publication number: 20100090325
    Abstract: In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 15, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yutaka UEMATSU, Yukitoshi HIROSE
  • Patent number: 7689944
    Abstract: A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: March 30, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuaki Katagiri, Satoshi Nakamura, Takashi Suga, Satoshi Isa, Yoji Nishio, Seiji Funaba, Yukitoshi Hirose
  • Patent number: 7681154
    Abstract: A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: March 16, 2010
    Assignees: Elpida Memory, Inc., Hitachi, Ltd.
    Inventors: Mitsuaki Katagiri, Satoshi Nakamura, Takashi Suga, Hiroya Shimizu, Satoshi Isa, Satoshi Itaya, Yukitoshi Hirose
  • Publication number: 20100013528
    Abstract: A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
    Type: Application
    Filed: July 16, 2009
    Publication date: January 21, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Yutaka Uematsu, Tatsuya Saito, Yoji Nishio, Yukitoshi Hirose
  • Publication number: 20090327981
    Abstract: Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 31, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Satoshi Nakamura, Tsutomu Hara, Mitsuaki Katagiri, Yukitoshi Hirose, Satoshi Itaya, Ken Iwakura