Patents by Inventor Yukitoshi Hirose
Yukitoshi Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7576421Abstract: A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.Type: GrantFiled: August 13, 2007Date of Patent: August 18, 2009Assignee: Elpida Memory, Inc.Inventor: Yukitoshi Hirose
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Publication number: 20090164724Abstract: A memory system according to the present invention copies data stored in memory modules to a hard disk device at each predetermined period, in replacing an arbitrary memory module, switches a bus from a unidirectional bus to a bi-directional bus, and at the time when an access to a memory module to be replaced is requested, accesses a storage area in the hard disk corresponding to an address space of the memory module. In addition, the memory system copies data corresponding to the address space of the memory module to be replaced from the hard disk device to a storage, and at the time when an access to the memory module is requested, accesses a storage area of the storage corresponding to the address space. Moreover, the memory system short-circuits bus connection which is disconnected by removing the memory module to be replaced.Type: ApplicationFiled: February 24, 2009Publication date: June 25, 2009Applicant: Elpida Memory, Inc.Inventor: Yukitoshi HIROSE
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Publication number: 20090102511Abstract: A semiconductor device of the invention has a plurality of P-channel transistors, to which resistance elements are inserted in series, prepared on a pull-up side of a driver such that an ON resistance value on the P-channel transistor side and a resistance value of the resistance element can be selected. In addition, also on a pull-down side of the driver, a plurality of N-channel transistors to which resistance elements are inserted in series are prepared such that an ON resistance value on the N-channel transistor side and a resistance value of the resistance element can be selected. A driver section having a linear current-voltage characteristic is realized by combination of those described.Type: ApplicationFiled: October 17, 2008Publication date: April 23, 2009Applicant: Elpida Memory, Inc.Inventor: Yukitoshi Hirose
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Publication number: 20090065774Abstract: The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.Type: ApplicationFiled: November 4, 2008Publication date: March 12, 2009Applicant: ELPIDA MEMORY INC.Inventor: Yukitoshi HIROSE
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Patent number: 7466158Abstract: The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.Type: GrantFiled: October 21, 2005Date of Patent: December 16, 2008Assignee: Elpida Memory, Inc.Inventor: Yukitoshi Hirose
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Publication number: 20080072194Abstract: A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad.Type: ApplicationFiled: September 13, 2007Publication date: March 20, 2008Applicants: ELPIDA MEMORY, INC., HITACHI, LTD.Inventors: Mitsuaki KATAGIRI, Satoshi Nakamura, Takashi Suga, Hiroya Shimizu, Satoshi Isa, Satoshi Itaya, Yukitoshi Hirose
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Patent number: 7319267Abstract: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer.Type: GrantFiled: March 1, 2007Date of Patent: January 15, 2008Assignee: Elpida Memory, Inc.Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Yukitoshi Hirose
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Publication number: 20070290317Abstract: A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.Type: ApplicationFiled: August 13, 2007Publication date: December 20, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Yukitoshi HIROSE
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Patent number: 7268420Abstract: A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.Type: GrantFiled: December 23, 2004Date of Patent: September 11, 2007Assignee: Elpida Memory, Inc.Inventor: Yukitoshi Hirose
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Patent number: 7253457Abstract: A semiconductor device, which may be changed to a mirror package after the assembly without having to reinstall bonding wires, comprises: a plurality of fixed external terminals which include a power supply external terminal and a ground potential external terminal and which are arranged symmetrically in fixed positions; a plurality of variable external terminals of different types which are arranged symmetrically; a plurality of reverse-polarity selection external terminals which are symmetrically arranged in fixed positions, and a signal switching circuit which switches the arrangement of the symmetrically arranged variable external terminal according to the setting of the selection terminal.Type: GrantFiled: August 12, 2002Date of Patent: August 7, 2007Assignee: Elpida Memory, Inc.Inventor: Yukitoshi Hirose
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Publication number: 20070145559Abstract: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer.Type: ApplicationFiled: March 1, 2007Publication date: June 28, 2007Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Yukitoshi Hirose
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Publication number: 20070057380Abstract: A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.Type: ApplicationFiled: August 29, 2006Publication date: March 15, 2007Inventors: Mitsuaki Katagiri, Satoshi Nakamura, Takashi Suga, Satoshi Isa, Yoji Nishio, Seiji Funaba, Yukitoshi Hirose
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Patent number: 7187069Abstract: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.Type: GrantFiled: November 5, 2004Date of Patent: March 6, 2007Assignee: Elpida Memory, Inc.Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Yukitoshi Hirose
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Publication number: 20060227587Abstract: Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.Type: ApplicationFiled: March 21, 2006Publication date: October 12, 2006Inventors: Satoshi Nakamura, Takashi Suga, Mitsuaki Katagiri, Yukitoshi Hirose
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Publication number: 20060087021Abstract: The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.Type: ApplicationFiled: October 21, 2005Publication date: April 27, 2006Inventor: Yukitoshi Hirose
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Publication number: 20060017144Abstract: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.Type: ApplicationFiled: November 5, 2004Publication date: January 26, 2006Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Yukitoshi Hirose
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Publication number: 20050139978Abstract: A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.Type: ApplicationFiled: December 23, 2004Publication date: June 30, 2005Applicant: ELPIDA MEMORY, INC.Inventor: Yukitoshi Hirose
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Publication number: 20040158675Abstract: A memory system according to the present invention copies data stored in memory modules to a hard disk device at each predetermined period, in replacing an arbitrary memory module, switches a bus from a unidirectional bus to a bi-directional bus, and at the time when an access to a memory module to be replaced is requested, accesses a storage area in the hard disk corresponding to an address space of the memory module. In addition, the memory system copies data corresponding to the address space of the memory module to be replaced from the hard disk device to a storage, and at the time when an access to the memory module is requested, accesses a storage area of the storage corresponding to the address space. Moreover, the memory system short-circuits bus connection which is disconnected by removing the memory module to be replaced.Type: ApplicationFiled: December 1, 2003Publication date: August 12, 2004Applicant: ELPIDA MEMORY, INC.Inventor: Yukitoshi Hirose
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Publication number: 20030038350Abstract: A semiconductor device, which may be changed to a mirror package after the assembly without having to reinstall bonding wires, comprises: a plurality of fixed external terminals which include a power supply external terminal and a ground potential external terminal and which are arranged symmetrically in fixed positions; a plurality of variable external terminals of different types which are arranged symmetrically; a plurality of reverse-polarity selection external terminals which are symmetrically arranged in fixed positions, and a signal switching circuit which switches the arrangement of the symmetrically arranged variable external terminal according to the setting of the selection terminal.Type: ApplicationFiled: August 12, 2002Publication date: February 27, 2003Applicant: ELPIDA MEMORY, INC.Inventor: Yukitoshi Hirose
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Patent number: 6448833Abstract: A delay circuit using MOS transistors for use of load capacitance which produces a stable delay effect for variations in signal voltage is provided. A gate of a P-type MOS transistor for load capacitance and a gate of an N-type MOS transistor for load capacitance are connected to a signal line. A resistor and CMOS inverters are used to apply a boosted voltage higher than a supply voltage VDD to a source-drain of the P-type MOS transistor for load capacitance and a substrate voltage lower than a ground voltage to a source-drain of the N-type MOS transistor for load capacitance. As a result, a gate voltage range for allowing the MOS transistors for load capacitance to have a capacitance is extended, and a stable delay effect is assured for a widened variation of signal current flowing on the signal line.Type: GrantFiled: March 6, 2001Date of Patent: September 10, 2002Assignee: NEC CorporationInventor: Yukitoshi Hirose