Patents by Inventor Yukiya Hirabayashi

Yukiya Hirabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6852653
    Abstract: A method of manufacturing a semiconductor substrate (7) includes the processes of: forming an insulation film (2) on a surface of a semiconductor substrate main body (1); forming an ion shield member (3) having a predetermined shape on the insulation film; implanting an ion into the semiconductor substrate main body from a side on which the insulation film is formed, to thereby form an ion implantation layer (1a, 1b); removing the ion shield member; laminating the insulation film and a support substrate (5) onto each other; and separating the semiconductor substrate main body from the support substrate at a portion of the ion implantation layer.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: February 8, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Yasushi Yamazaki, Yukiya Hirabayashi
  • Publication number: 20040141137
    Abstract: An electro-optical device includes an active matrix substrate having on the same plane a plurality of scanning lines, a plurality of signal lines provided to intersect the scanning lines, a plurality of pixel electrodes provided at the intersection portions of the scanning lines and the signal lines, and a peripheral driving circuits to matrix drive the pixel electrodes; a counter substrate having a common electrode on one surface and facing the active matrix substrate so that the common electrode is opposite to the pixel electrodes; and a liquid crystal layer interposed between the active matrix substrate and the counter substrate. In the common electrode, a portion, where the common electrode overlaps with the peripheral driving circuit or with wiring lines to supply signals to the peripheral driving circuit in plan view, is removed.
    Type: Application
    Filed: September 10, 2003
    Publication date: July 22, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yukiya Hirabayashi
  • Publication number: 20040109128
    Abstract: Methods and systems are provided for securely preventing cracking or peeling of an insulating film in the periphery of a cutting portion of cutting short-circuit wiring by etching in a substrate, such as a liquid crystal device substrate that includes short-circuit wiring for a measure against static electricity. In particular, in the liquid crystal device substrate, cutting holes are provided by etching in a first interlayer insulating film and a second interlayer insulating film, which cover short-circuit wiring provided as electrostatic measure wiring, for cutting the short-circuit wiring. An etching stop layer made of a single crystal silicon film having resistance to etching of the second interlayer insulating film is formed in a wider range than the cutting holes between the short-circuit wiring and the buried oxide film.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 10, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yukiya Hirabayashi
  • Patent number: 6744198
    Abstract: The invention provides a method for manufacturing a display device that includes a light-transmitting substrate and, above the light-transmitting substrate, a plurality of light-emitting elements arrayed in a plane, driving elements connected to the light-emitting elements, a bank layer disposed in the boundary areas between the plurality of light-emitting elements, and wires connected to the driving elements. In this method, the wires are formed by patterning a light-shielding, conductive layer on the light-transmitting substrate so as to have a shape in plan view corresponding to the shape of the bank layer in plan view. Then, the wires, acting as a mask, are exposed from the rear surface of the substrate to form the bank layer by self-aligning above the wires. Then, the light-emitting elements are formed in the areas surrounded by the bank layer.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: June 1, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Patent number: 6734940
    Abstract: Methods and systems are provided for securely preventing cracking or peeling of an insulating film in the periphery of a cutting portion of cutting short-circuit wiring by etching in a substrate, such as a liquid crystal device substrate that includes short-circuit wiring for a measure against static electricity. In particular, in the liquid crystal device substrate, cutting holes are provided by etching in a first interlayer insulating film and a second interlayer insulating film, which cover short-circuit wiring provided as electrostatic measure wiring, for cutting the short-circuit wiring. An etching stop layer made of a single crystal silicon film having resistance to etching of the second interlayer insulating film is formed in a wider range than the cutting holes between the short-circuit wiring and the buried oxide film.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: May 11, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Patent number: 6661025
    Abstract: A method of manufacturing an electro-optical apparatus substrate (10), includes the processes of: forming a light shield layer on one surface of an optically transparent substrate; patterning the light shield layer to thereby form a patterned light shield layer (11a) at least in a formation region of each transistor element (30) to be formed; forming a first insulation layer (12A) above the one surface of the optically transparent substrate above which the patterned light shield layer has been formed; forming a second insulation layer (12B) having a polishing rate lower than that of the first insulation layer, on the first insulation layer; polishing a surface of the second insulation layer; laminating a single crystal silicon layer (206) on the polished surface of the second insulation layer; and forming the each transistor element by using the single crystal silicon layer.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: December 9, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Patent number: 6628367
    Abstract: The invention provides an electrooptical device, such as a liquid-crystal device that presents a high-contrast, bright and high-quality image, by reducing a malfunction due to a transverse electric field in an electrooptical material, such as a liquid crystal. The electrooptical device includes pixel electrodes on a TFT array substrate and a counter electrode on a counter substrate. Arranged beneath the pixel electrodes in the TFT array substrate are protrusions in an area facing a spacing between adjacent pixel electrodes. The method for manufacturing such an electrooptical device includes: forming a pattern including a wiring, a TFT, etc. on the TFT array substrate; planarizing the surface of a laminate of the substrate including the pattern; and forming the protrusion by subjecting the planarized surface to photolithographic and etching processes.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: September 30, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Yasushi Yamazaki
  • Patent number: 6593626
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: July 15, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Patent number: 6594064
    Abstract: To prevent the substrate floating effect that is caused when a transistor channel region fabricated of a monocrystal silicon layer covered with an insulator is in a floating state, and to stabilize the electrical characteristics of the transistor. A channel region of a semiconductor layer includes an extension portion. The end of the extension portion is connected to a contact hole. The contact hole is in turn connected to an interconnect line. The interconnect line is configured with one end thereof connected to the contact hole and with the other end connected to a contact hole leading to a light-shielding layer.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: July 15, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Publication number: 20030116802
    Abstract: A method of manufacturing a semiconductor substrate includes the processes of: forming an insulation film on a surface of a semiconductor substrate main body; forming an ion shield member having a predetermined shape on the insulation film; implanting an ion into the semiconductor substrate main body from a side on which the insulation film is formed, to thereby form an ion implantation layer; removing the ion shield member; laminating the insulation film and a support substrate onto each other; and separating the semiconductor substrate main body from the support substrate at a portion of the ion implantation layer.
    Type: Application
    Filed: December 2, 2002
    Publication date: June 26, 2003
    Applicant: Seiko Epson Corporation
    Inventors: Yasushi Yamazaki, Yukiya Hirabayashi
  • Patent number: 6577371
    Abstract: In a liquid crystal panel substrate having a layered film structure of interlayer insulation films and metal layers alternately formed on a semiconductor substrate provided with a transistor region for pixel selection thereon, to provide a configuration for achieving a uniform polishing rate without thickening of the interlayer insulation film to be polished. A liquid crystal panel substrate is provided with a shading film 12 composed of a second metal layer in a pixel region, a second interlayer insulation film 11 under the shading film, a wiring film 10 composed of a first metal layer under the second interlayer insulation film, a pixel electrode composed of a third metal layer on a third interlayer insulation film 13 on the shading film, and a connecting plug 15 connecting the wiring film 10 and the pixel electrode through an opening provided in the shading film 12.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: June 10, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Publication number: 20020140343
    Abstract: A method for manufacturing a display device including a light-transmitting substrate and, above the light-transmitting substrate, a plurality of light-emitting elements arrayed in a plane, driving elements connected to the light-emitting elements, a bank layer disposed in the boundary areas between the plurality of light-emitting elements, and wires connected to the driving elements. In this method, the wires are formed by patterning a light-shielding, conductive layer on the light-transmitting substrate so as to have a shape in plan view corresponding to the shape of the bank layer in plan view. Then, the wires, acting as a mask, are exposed from the rear surface of the substrate to form the bank layer by self-aligning above the wires. Then, the light-emitting elements are formed in the areas surrounded by the bank layer.
    Type: Application
    Filed: March 19, 2002
    Publication date: October 3, 2002
    Applicant: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Publication number: 20020097367
    Abstract: In a liquid crystal panel substrate having a layered film structure of interlayer insulation films and metal layers alternately formed on a semiconductor substrate provided with a transistor region for pixel selection thereon, to provide a configuration for achieving a uniform polishing rate without thickening of the interlayer insulation film to be polished. A liquid crystal panel substrate is provided with a shading film 12 composed of a second metal layer in a pixel region, a second interlayer insulation film 11 under the shading film, a wiring film 10 composed of a first metal layer under the second interlayer insulation film, a pixel electrode composed of a third metal layer on a third interlayer insulation film 13 on the shading film, and a connecting plug 15 connecting the wiring film 10 and the pixel electrode through an opening provided in the shading film 12.
    Type: Application
    Filed: February 8, 2002
    Publication date: July 25, 2002
    Applicant: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Publication number: 20020093019
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 18, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Patent number: 6403395
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: June 11, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Publication number: 20020047159
    Abstract: A method of manufacturing a semiconductor substrate (7) includes the processes of: forming an insulation film (2) on a surface of a semiconductor substrate main body (1); forming an ion shield member (3) having a predetermined shape on the insulation film; implanting an ion into the semiconductor substrate main body from a side on which the insulation film is formed, to thereby form an ion implantation layer (1a, 1b); removing the ion shield member; laminating the insulation film and a support substrate (5) onto each other; and separating the semiconductor substrate main body from the support substrate at a portion of the ion implantation layer.
    Type: Application
    Filed: October 5, 2001
    Publication date: April 25, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yasushi Yamazaki, Yukiya Hirabayashi
  • Patent number: 6373544
    Abstract: In a liquid crystal panel substrate having a layered film structure of interlayer insulation films and metal layers alternately formed on a semiconductor substrate provided with a transistor region for pixel selection thereon, to provide a configuration for achieving a uniform polishing rate without thickening of the interlayer insulation film to be polished. A liquid crystal panel substrate is provided with a shading film 12 composed of a second metal layer in a pixel region, a second interlayer insulation film 11 under the shading film, a wiring film 10 composed of a first metal layer under the second interlayer insulation film, a pixel electrode composed of a third metal layer on a third interlayer insulation film 13 on the shading film, and a connecting plug 15 connecting the wiring film 10 and the pixel electrode through an opening provided in the shading film 12.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: April 16, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Publication number: 20020037600
    Abstract: A method of manufacturing an electro-optical apparatus substrate (10), includes the processes of: forming a light shield layer on one surface of an optically transparent substrate; patterning the light shield layer to thereby form a patterned light shield layer (11a) at least in a formation region of each transistor element (30) to be formed; forming a first insulation layer (12A) above the one surface of the optically transparent substrate above which the patterned light shield layer has been formed; forming a second insulation layer (12B) having a polishing rate lower than that of the first insulation layer, on the first insulation layer; polishing a surface of the second insulation layer; laminating a single crystal silicon layer (206) on the polished surface of the second insulation layer; and forming the each transistor element by using the single crystal silicon layer.
    Type: Application
    Filed: September 5, 2001
    Publication date: March 28, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yukiya Hirabayashi
  • Patent number: 6358759
    Abstract: A electro-optical device and manufacturing method are provided for an electro-optical device that has the step of forming a light shielding layer on one side of a light transmissive substrate, patterning the light shielding layer, forming an insulating layer on the patterned light shielding layer, planarizing the insulating layer, bonding a model crystalline silicon layer on the surface of the planarized insulating layer, and forming a transistor element from the monocrystalline silicon layer, wherein the patterned light shielding layer is arranged in an area facing the transistor element and in a peripheral area surrounding the transistor element.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: March 19, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Publication number: 20020021402
    Abstract: The invention provides an electrooptical device, such as a liquid-crystal device that presents a high-contrast, bright and high-quality image, by reducing a malfunction due to a transverse electric field in an electrooptical material, such as a liquid crystal. The electrooptical device includes pixel electrodes on a TFT array substrate and a counter electrode on a counter substrate. Arranged beneath the pixel electrodes in the TFT array substrate are protrusions in an area facing a spacing between adjacent pixel electrodes. The method for manufacturing such an electrooptical device includes: forming a pattern including a wiring, a TFT, etc. on the TFT array substrate; planarizing the surface of a laminate of the substrate including the pattern; and forming the protrusion by subjecting the planarized surface to photolithographic and etching processes.
    Type: Application
    Filed: June 11, 2001
    Publication date: February 21, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Yasushi Yamazaki