Patents by Inventor Yukiya Hirabayashi

Yukiya Hirabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020008240
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Application
    Filed: August 28, 2001
    Publication date: January 24, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Patent number: 6331473
    Abstract: A bonded SOI substrate is disclosed using a transparent electrode without causing generation of a leakage current by light in semiconductive devices formed on the substrate when light is incident on the rear face of the substrate, resulting in decreased deterioration of device characteristics and malfunction. A shielding layer is formed between a transparent supporting substrate and a single-crystal silicon layer of an SOI substrate that can shield light incident on the rear face of the substrate. The light shielding layer is preliminarily formed on the supporting substrate prior to bonding of the single-crystal silicon layer to the supporting substrate in an SOI production process by a bonding method.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: December 18, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Yukiya Hirabayashi
  • Patent number: 6320204
    Abstract: A channel region of a semiconductor layer has an extending portion. The terminal of the extending portion is connected to a first contact hole. The first contact hole is connected to a connecting line. The connecting line is connected to the first contact hole at one end, as described above, extends directly above a capacitor line in the Y direction, and is connected to the capacitor line via a second contact hole at this position.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: November 20, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Yukiya Hirabayashi, Shigenori Katayama, Masahiro Yasukawa
  • Publication number: 20010038485
    Abstract: To prevent the substrate floating effect that is caused when a transistor channel region fabricated of a monocrystal silicon layer covered with an insulator is in a floating state, and to stabilize the electrical characteristics of the transistor. A channel region of a semiconductor layer includes an extension portion. The end of the extension portion is connected to a contact hole. The contact hole is in turn connected to an interconnect line. The interconnect line is configured with one end thereof connected to the contact hole and with the other end connected to a contact hole leading to a light-shielding layer.
    Type: Application
    Filed: April 11, 2001
    Publication date: November 8, 2001
    Inventor: Yukiya Hirabayashi
  • Publication number: 20010028415
    Abstract: Methods and systems are provided for securely preventing cracking or peeling of an insulating film in the periphery of a cutting portion of cutting short-circuit wiring by etching in a substrate, such as a liquid crystal device substrate that includes short-circuit wiring for a measure against static electricity. In particular, in the liquid crystal device substrate, cutting holes are provided by etching in a first interlayer insulating film and a second interlayer insulating film, which cover short-circuit wiring provided as electrostatic measure wiring, for cutting the short-circuit wiring. An etching stop layer made of a single crystal silicon film having resistance to etching of the second interlayer insulating film is formed in a wider range than the cutting holes between the short-circuit wiring and the buried oxide film.
    Type: Application
    Filed: February 6, 2001
    Publication date: October 11, 2001
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yukiya Hirabayashi