Abstract: Noise is reduced in a solid-state image capturing element provided with an ADC for each column. An analog-to-digital converter increases or decreases an analog signal using an analog gain selected from among a plurality of analog gains, and converts the increased or decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, one of a test signal having a predetermined level and a pixel signal to the analog-to-digital converter. In a case where a test signal is inputted, a correction value calculation section obtains, from the analog signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section, when inputted with the pixel signal after the correction value is outputted, corrects the digital signal using the correction value.

Abstract: Noise is reduced in a solid-state image capturing element provided with an ADC for each column. An analog-to-digital converter increases or decreases an analog signal using an analog gain selected from among a plurality of analog gains, and converts the increased or decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, one of a test signal having a predetermined level and a pixel signal to the analog-to-digital converter. In a case where a test signal is inputted, a correction value calculation section obtains, from the analog signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section, when inputted with the pixel signal after the correction value is outputted, corrects the digital signal using the correction value.

Abstract: An imaging device according to the present disclosure includes a plurality of pixel units each including a first pixel unit and a second pixel unit and a vertical signal line, in which each of the first pixel unit and the second pixel unit includes an amplification transistor, a selection transistor connected between the amplification transistor and the vertical signal line, and a connection unit that selectively connects between a common connection node of the amplification transistor and the selection transistor of the first pixel unit and a common connection node of the amplification transistor and the selection transistor of the second pixel unit.

Abstract: [Problem] To provide an imaging device capable of generating an image with reduced noise. [Solution] Provided is an imaging device including: a signal output unit configured to output a predetermined signal; a switch unit configured to output either an output from the signal output unit or an output from a pixel array configured to output a pixel signal by photoelectric conversion in a switching manner; and a signal processing unit configured to execute signal processing using an output from the switch unit.

Abstract: An imaging device according to the present disclosure includes a plurality of pixel units each including a first pixel unit and a second pixel unit and a vertical signal line, in which each of the first pixel unit and the second pixel unit includes an amplification transistor, a selection transistor connected between the amplification transistor and the vertical signal line, and a connection unit that selectively connects between a common connection node of the amplification transistor and the selection transistor of the first pixel unit and a common connection node of the amplification transistor and the selection transistor of the second pixel unit.

Abstract: According to one embodiment, a solid-state imaging device includes a pixel array, a scanning circuit, signal lines, processing circuits, and connection parts. One processing circuit and the signal lines are provided per one pixel column of the pixel array. The signal lines include a first signal line and a second signal line. Each pixel column includes first pixels and second pixels. The first pixels are configured to output pixel signals to the first signal line. The second pixels are configured to output pixel signals to the second signal line. When the scanning circuit simultaneously selects a first pixel row and a second pixel row, the connection parts connect the first signal line and the second signal line of each pixel column to different processing circuits. The first pixel row includes the first pixels. The second pixel row includes the second pixels.

Abstract: According to one embodiment, a signal processing circuit includes a defect correction circuit. The defect correction circuit includes a color difference calculation part, a color difference sorting part, and a correction amount calculation part. The color difference calculation part is configured to calculate a difference between a signal level of a first pixel and a signal level of a second pixel in a pixel group. The pixel group includes pixels juxtaposed in a horizontal direction with a target pixel at a center. The correction amount calculation part is configured to calculate a correction amount for the target pixel, based on a difference chosen by the color difference sorting part and a signal level of a second pixel adjacent to the target pixel.

Abstract: According to one embodiment, an image processing device includes a line memory that stores an input image by a plurality of rows; a defect correcting circuit that performs defect correction on the input image based on image data stored in the line memory; a binning circuit that generates a low pass image having a lower spatial frequency than the input image by binning the input image subjected to the defect correction; a frame buffer that stores the low pass image; a filter that generates a high pass image having a higher spatial frequency than the low pass image by filtering the input image subjected to the defect correction; and a mixing circuit that mixes the low pass image with the high pass image.

Abstract: According to one embodiment, an image processing apparatus includes a defect correcting circuit. The defect correcting circuit includes a defect judging unit, a first correcting unit, and a second correcting unit. The defect judging unit performs defect judgment on a target pixel. The first correcting unit performs replacement of a pixel value of the target pixel detected as a defect based on a result of the defect judgment. The second correcting unit performs an interpolating process of a pixel value on a designated pixel. The designated pixel is the pixel of which positional information is registered in advance as a defect. When the second correcting unit performs the interpolating process, the defect judging unit performs the defect judgment according to the pixel value subjected to the interpolating process.

Abstract: According to one embodiment, a solid-state imaging apparatus includes a pixel array, a first vertical signal line, a second vertical signal line, and a control unit. Each of cells includes a plurality of pixels. The first vertical signal line is connected to first cells. The second vertical signal line is connected to second cells. The control unit generates a timing signal. In each of the cells, two pixels are arrayed in a horizontal direction and at least two pixels are arrayed in a vertical direction. The control unit prioritizes ordering of pixels selected from the plurality of pixels to cause timings to read signals from the selected pixels to continue in the vertical direction. The control unit generates a timing signal that prioritizes ordering of the selected pixels over other pixels.

Abstract: According to one embodiment, a solid-state imaging device comprises a pixel array wherein unit patterns are placed repeatedly the unit pattern along vertical and horizontal directions. The unit pattern has at least four pixels arranged vertically and two pixels arranged horizontally. The unit pattern is formed of pixels of a first group including two first green pixels and pixels of a second group including two second green pixels. The two first green pixels are arranged vertically with one of a red pixel and a blue pixel in between, and the two second green pixels are arranged vertically with one of a red pixel and a blue pixel in between.

Abstract: According to one embodiment, a solid-state imaging device includes a high dynamic range (HDR) synthesizing unit. The HDR synthesizing unit synthesizes a first image signal from a first pixel and a second image signal from a second pixel. The first pixel is a pixel to which a first exposure time is applied. The second pixel is a pixel to which a second exposure time is applied. The second exposure time is shorter than the first exposure time. The first and second horizontal lines form a periodic array. The first horizontal line is a horizontal line formed by the first pixels. The second horizontal line is a horizontal line formed by the second pixels. In the periodic array, a combination of the first horizontal lines and the second horizontal lines of the number which is twice the number of first horizontal lines is formed as units.

Abstract: According to one embodiment, a light receiver includes a light reception module, a multi-exposure area selector, a multi-exposure controller, and a readout module. The light reception module includes N lines, each of the N lines having a plurality of light receiving elements. The multi-exposure area selector is configured to select one or a plurality of single-exposure lines and one or a plurality of multi-exposure lines. The multi-exposure controller is configured to, per the unit time, perform an exposure on the single-exposure lines one time for a first exposure time; and a first exposure and a second exposure on the multi-exposure lines. The readout module is configured to read exposure amounts of the lines line by line. The multi-exposure controller is configured to start the second exposure on the multi-exposure lines before reading of the exposure amounts of all the single-exposure lines is completed.

Abstract: According to one embodiment, in a pixel array unit, pixels configured to accumulate photoelectrically-converted charges are arranged in a matrix shape. A binning control unit performs control to lump together several pixels among the pixels between different lines of the pixel array unit. A frame-read control unit thins out and reads the lines to vary thinning positions of the lines lumped together by the binning control unit among two or more frames. A reconfiguration processing unit combines the two or more frames, in which the thinning positions are different, to thereby configure one frame.

Abstract: According to one embodiment, in a pixel array section, pixels that accumulate photoelectrically-converted charges are arranged in a matrix shape. An exposure-period control section controls an exposure period of the pixels for each of fields and controls readout timing such that interlace readout is performed from the pixel array section. A charge-discharging control section performs discharge control for charges accumulated in the pixels in a non-exposure period of the pixels.

Abstract: According to embodiment, an image processing device includes a black level correcting section. The black level correcting section includes a first input restricting unit and a second input restricting unit. The second input restricting unit performs a second input restriction, having a second signal level range including a moving average as a reference, on a black level signal subjected to a first input restriction by the first input restricting unit. A correction amount calculation unit calculates a difference of an average of signal values subjected to the second input restriction and a black level standard value as a correction value to apply on an effective pixel signal.

Abstract: According to an embodiment, a high dynamic range synthesizing circuit includes an interpolation processing unit, a blur detection unit and a mix processing unit. The interpolation processing unit generates an interpolation signal. The blur detection unit uses a first image signal and a second image signal a signal level of which is adjusted for detecting the amount of blur. The mix processing unit performs processing of mixing the second image signal into the interpolation signal. The mix processing unit applies a weight of the second image signal depending on the amount of blur to the interpolation signal by the mix processing.

Abstract: According to one embodiment, a solid-state imaging device includes a pixel array, a digital gain circuit, and a shading correction circuit. In the pixel array, pixels that accumulate photoelectrically converted charge are arranged in a matrix and the pixel array can control an exposure time of the pixels for each line. The digital gain circuit adjusts a digital gain of an output signal of the pixel array. The shading correction circuit corrects shading of the pixel array by controlling the exposure time of the pixels and the digital gain.

Abstract: According to one embodiment, a high dynamic range synthesizing circuit includes an interpolation processing unit. The interpolation processing unit generates an interpolated signal for a first pixel, which is set as a target pixel, through an interpolation process using a second image signal from a second pixel which is a peripheral pixel. The interpolation processing unit generates an interpolated signal for the second pixel, which is set as a target pixel, through an interpolation process using the first image signal from the first pixel which is a peripheral pixel.

Abstract: According to embodiments, an image processing apparatus includes an image signal holding unit. The image processing apparatus uses an image signal passing through the common image signal holding unit to generate first, second and third correction values. The first correction value is a signal value applied to a pixel in which saturation of an output occurs in a saturation determination. The second correction value is a signal value subjected to a noise cancellation process. The third correction value is a signal value applied to a pixel in which defect occurs in a defect determination.