Abstract: The present disclosure provides a package including a die, a first leadframe and a second leadframe. The first leadframe and the second leadframe are stacked and bonded together by using adhering substance to form a final leadframe. The die is bonded to the final leadframe. By using the package of the embodiments, the package includes appropriate signal transmission paths and multi-directional heat dissipation paths.

Abstract: A method for prolonging telomere length in a subject is disclosed. The method comprises administering a composition including Salvia miltiorrhiza extract, wheat ?-amylase inhibitor, and probiotic powder. Administration of the composition prolongs telomere length and provides cellular effects associated with prolonged telomere length, such as a reduction in telomere-associated cellular age.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: An IC package structure with connections is provided in the present disclosure, including a die bonded to a leadframe, a plurality of connections bonded to the leadframe, a molding compound formed on the leadframe, a metal layer formed on the molding compound and electrically connecting with the connections, and an electronic component mounted on the metal layer.

Abstract: A testing method for use in semiconductor device testing, includes: performing at least one test item from a set of test items on a semiconductor device under a first environmental condition; generating, via a machine learning model and based on a test result of the at least one test item, a qualification result predictive of at least one test result for one or more test items from the set of test items when performed on the semiconductor device under a second environmental condition; and determining, based on the qualification result, whether to perform the one or more test items from the set of test items on the semiconductor device under the second environmental condition.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: A dynamic voltage stress (DVS) condition optimization includes selecting a testing block from a plurality of blocks in a die of a wafer, acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature according to the testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures according to the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer according to the DVS block target temperature.

Abstract: A method for culturing stem cells is used to solve the problem of loss of stem cell functionality after passaging. The method includes forming a mixed solution by adding an extract of Salvia miltiorrhiza into a basal medium. The stem cells are then cultured in the mixed solution. By the use of the extract of Salvia miltiorrhiza, division and differentiation capacities of the stem cells can be maintained even after passaging. The mixed solution for culturing the stem cells is also disclosed.

Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

Abstract: A dynamic voltage stress (DVS) condition optimization includes selecting a testing block from a plurality of blocks in a die of a wafer, acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature according to the testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures according to the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer according to the DVS block target temperature.

Abstract: A dynamic voltage stress (DVS) condition optimization includes selecting a testing block from a plurality of blocks in a die of a wafer, acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature based on the testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer based on the DVS block target temperature.

Abstract: A die-level parametric prediction boosting method includes acquiring a wafer map having a plurality of dies, selecting a die from the plurality of dies, inputting physical location parametric data of the die and a plurality of electrical parametric features of the die to a training model, and generating predicted data of the die by the training model according to the physical location parametric data and the plurality of electrical parametric features.

Abstract: A die-level parametric prediction boosting method includes acquiring mass production data of a plurality of dies, identifying a comprehensive indicator of each die according to the mass production data, generating a wafer map distribution of the plurality of dies according to a plurality of comprehensive indicators, partitioning the plurality of dies into at least two die clustering groups, and inputting a plurality of electrical parametric features of each die clustering group to a training model for generating predicted data of each die clustering group.

Abstract: An anti-aging composition is used to lengthen the telomere. The anti-aging composition comprises: 5-20 wt % of an extract of Salvia miltiorrhiza, 25-40 wt % of an ?-amylase inhibitor and 50-60 wt % of probiotics comprising a Bifidobacterium animalis subsp. Lactis and a Lacticaseibacillus rhamnosus. The probiotics have a concentration of 1×1010CFU per gram of the anti-aging composition.

Abstract: In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.

Abstract: An adaptive minimum voltage aging margin prediction method includes acquiring characteristic data of a plurality of dies in a testing line, predicting a wear-out failure rate of each module of the plurality of dies according to the characteristic data by using a neural network, and predicting a minimum voltage aging margin of the each module according to the wear-out failure rate of the each module by using the neural network.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure also includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials, and the first oxide layer is in direct contact with the isolation layer, and a sidewall surface of the S/D structure is aligned with a sidewall surface of the first oxide layer.