Abstract: The present disclosure relates to user-mode interrupt request processing methods and apparatuses. In one example method, a central processing unit (CPU) in a kernel mode runs a second interrupt exception handler that does not include a kernel address to determine a user-mode interrupt handler corresponding to a user-mode interrupt request, switches to a user mode by using a first privilege level without context recovery, further runs the user-mode interrupt handler in the user mode, and then switches to the kernel mode by using a second privilege level without context storage.

Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

Abstract: An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.

Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.

Abstract: An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.

Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).

Abstract: An apparatus comprising a first electrical driver configured to generate a first binary voltage signal according to first data, a second electrical driver configured to generate a second binary voltage signal according to second data, wherein the first data and the second data are different, and a first optical waveguide arm coupled to the first electrical driver and the second electrical driver, wherein the first optical waveguide arm is configured to shift a first phase of a first optical signal propagating along the first optical waveguide arm according to a first voltage difference between the first binary voltage signal and the second binary voltage signal to produce a first multi-level phase-shifted optical signal.

Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.

Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).

Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.

Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.