Abstract: An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.

Abstract: An apparatus comprising a first electrical driver configured to generate a first binary voltage signal according to first data, a second electrical driver configured to generate a second binary voltage signal according to second data, wherein the first data and the second data are different, and a first optical waveguide arm coupled to the first electrical driver and the second electrical driver, wherein the first optical waveguide arm is configured to shift a first phase of a first optical signal propagating along the first optical waveguide arm according to a first voltage difference between the first binary voltage signal and the second binary voltage signal to produce a first, multi-level phase-shifted optical signal.

Abstract: A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed.

Abstract: A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed.

Abstract: A system and corresponding method for generating multiple phases within a single clock cycle of an input signal is disclosed. The method includes the steps of generating a plurality of output signals from an input source signal, where each of the plurality of output signals represents a phase-shifted version of the input signal. Next, select a pair of signals from the plurality of output signals to act as clock signals, where the selected pair of clock signals define the operating region within which the multiple phases are bounded. Then, provide a pair of complementary weighted bias currents in response to a control signal, where each of the complementary bias currents is used to generate the multiple phases of the present invention. Thereafter, the pair of weighted bias currents presented to a node are adjusted in response to the selected pair of clock signals, where the selected pair of clock signals operates to adjust the rate of change of the weighted bias currents.