Abstract: Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

Abstract: A method for manufacturing a semiconductor device includes: forming a channel including a semiconductor material; forming two intermediate conductive layers in contact with the channel and spaced apart from each other; and forming two conductive contacts respectively on the two intermediate conductive layers. Each of the intermediate conductive layers includes at least one stacking unit. The at least one stacking unit includes two first metal oxide layers spaced apart from each other and a second metal oxide layer disposed between the two first metal oxide layers and extending along a lengthwise line such that the two first metal oxide layers are opposite to each other relative to the lengthwise line. Each of the first metal oxide layers includes first metal atoms. The second metal oxide layer includes second metal atoms that are different from the first metal atoms.

Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Abstract: A semiconductor structure includes a base structure having a conductive feature therein, a transistor disposed above the base structure, a capacitor disposed on the transistor, and an interconnecting routing that interconnects the second electrode with the conductive feature. The transistor includes a gate electrode, a gate dielectric, a channel spaced apart from the gate electrode through the gate dielectric, and two contact structures connected to the channel and spaced apart from each other. Each of the two contact structures includes a main body, and a protection layer that includes a transition metal which is one of elements of groups 3 to 12 in periods 5 to 7, elements of lanthanide series, and elements of actinide series. The capacitor includes a first electrode connected to one of the two contact structures of the transistor, a second electrode, and a dielectric interposed between the first electrode and the second electrode.

Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer and a first alignment layer. The first alignment layer is disposed between the first electrode layer and the ferroelectric layer, and the ferroelectric layer and the first alignment layer have the same crystal lattice orientation. In some embodiments, a material of the first alignment layer has a band gap smaller than 50 meV.

Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

Abstract: A memory device includes a memory cell having a first transistor, a second transistor, a first capacitor and a second capacitor coupled with each other into a data storage circuit configured to store a datum. The memory cell further has a third transistor and a fourth transistor coupled with each other into a comparison circuit configured to perform a comparison of the datum stored in the data storage circuit with a search input datum. The memory device further includes a back-end-of-line (BEOL) structure. The BEOL structure includes at least a part of the memory cell.

Abstract: Oxide semiconductor ferroelectric field effect transistors (OS-FeFETs) and method of forming the same are provide. A device disclosed herein includes an electrode in a first dielectric layer, a ferroelectric layer over the electrode and the first dielectric layer, a high-k dielectric layer over the ferroelectric layer, an oxide semiconductor layer over the high-k dielectric layer, a second dielectric layer over the oxide semiconductor layer and the high-k dielectric layer, and a first contact feature and a second contact feature extending through the second dielectric layer to contact the oxide semiconductor layer.

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

Abstract: A multiple-layer hydrogen barrier stack may be included between a non-volatile memory structure and conductive structures in an interconnect structure in a semiconductor device. The multiple-layer hydrogen barrier stack may minimize and/or prevent hydrogen diffusion into one or more layers of the non-volatile memory structure such as a metal-oxide channel of the non-volatile memory structure. The multiple-layer hydrogen barrier stack may include a hydrogen absorption layer and a hydrogen blocking layer on the hydrogen absorption layer. The hydrogen blocking layer blocks or resists diffusion of hydrogen through the conductive structures into the non-volatile memory structure. The hydrogen absorption layer may absorb any hydrogen atoms that might diffuse through the hydrogen blocking layer.

Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.

Abstract: A method is provided. The method includes applying a first pulse to a ferroelectric memory device, measuring a memory window metric of the ferroelectric memory device, and applying a second pulse to the ferroelectric memory device. The first pulse may have a first voltage magnitude. The second pulse may have a second voltage magnitude. The second voltage magnitude may be determined based at least in part on the measured memory window metric.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Abstract: Provided is a centrifugal heat dissipation fan including a housing and an impeller. The impeller is disposed in the housing. The impeller has a hub and multiple blades disposed surrounding the hub. Every two adjacent blades have different blade structures relative to the housing such that the blade structures pass by a fixed position of the housing and generate blade tones of varying frequencies when the impeller rotates.

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.