Patents by Inventor Yun Chen

Yun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250254897
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor structure. The transistor includes a gate electrode material. The capacitor structure includes a first electrode and a second electrode including the gate electrode material. The capacitor structure also includes a plurality of first conductive features disposed over the first electrode and a plurality of conductive vias disposed over a corresponding one of the plurality of first conductive features. The capacitor structure further includes a third electrode over the plurality of conductive vias and electrically connected to the first electrode through the plurality of first conductive features and the plurality of conductive vias.
    Type: Application
    Filed: February 6, 2024
    Publication date: August 7, 2025
    Inventors: SHIH-EN LAI, KAU-CHU LIN, CHAN-YU HUNG, FEI-YUN CHEN
  • Publication number: 20250246478
    Abstract: Semiconductor devices and methods for forming semiconductor devices are provided. A method includes forming a shallow trench isolation (STI) feature; forming a mask layer over the STI feature; depositing sacrificial material over the mask layer; and etching the sacrificial material to form sacrificial structures over the mask layer, wherein the mask layer prevents etching of the STI feature while etching the sacrificial material.
    Type: Application
    Filed: January 30, 2024
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Chen Teng, Sen-Hong Syue, Chi On Chui
  • Publication number: 20250227963
    Abstract: Transistors with strained source drain (SDD) structures are suitable for high voltage applications. A gate stack is present upon the substrate that includes a gate dielectric layer and a gate structure upon the gate dielectric layer. A gate spacer is present on the sidewalls of the gate stack. Two lightly doped drain (LDD) regions extend from below the gate stack towards opposite sides of the gate stack. A plurality of strained source and drain (SSD) structures are present within each LDD region. The SSD structures do not extend below the gate spacers. The transistor can be used in high voltage devices and still avoid junction breakdown.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 10, 2025
    Inventors: Yi-Huan Chen, Jhu-Min Song, Chien-Chih Chou, Fei-Yun Chen
  • Publication number: 20250216338
    Abstract: A micro LED detection device comprises a device table provided with a stepper driving module and a first detection module and a second detection module linked with the stepper driving module, the first detection module has a first microscope lens and laser generators, the second detection module has a second microscope lens; a first air-float platform, a second air-float platform, and a third air-float platform air floated on the device table and respectively connected to first and second linear driving modules and at least one third linear driving module, the third air-float platform has a detection platform; and a detection host having AI judgment units and a processing unit, the AI judgment unit receives a captured picture and generates at least one judgment signal from the captured picture, thereby artificial intelligence is used to perform brightness level discrimination, surface defect and etching depth detection on a micro LED wafer.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: KUAN-HAN CHEN, YING-YUN CHEN
  • Patent number: 12347696
    Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
  • Publication number: 20250212437
    Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming an interlayer dielectric (ILD) layer over the fin around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the fin to cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first and the second dielectric plugs; etching, using the patterned mask layer as an etching mask, the segment of the gate structure to form a recess in the gate structure; extending the recess into the fin by performing an anisotropic etching process to deepen the recess; and after extending the recess, filling the recess with a dielectric material.
    Type: Application
    Filed: March 19, 2024
    Publication date: June 26, 2025
    Inventors: Tzu-Ging Lin, Ya-Yi Tsai, Yun-Chen Wu, Shu-Yuan Ku
  • Publication number: 20250204019
    Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.
    Type: Application
    Filed: February 26, 2025
    Publication date: June 19, 2025
    Inventors: Yun Chen Teng, Chen-Fong Tsai, Li-Chi Yu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20250191968
    Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.
    Type: Application
    Filed: January 29, 2025
    Publication date: June 12, 2025
    Inventors: Chieh Chang, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12324538
    Abstract: A computer-implemented method for determining a scaled cooking time for operating a cooking apparatus includes acquiring a recipe having information associated with one or more food ingredients, a recipe serving size, and a recipe cooking time, and acquiring a target serving size. The method further includes determining a recipe scale factor based on the target serving size and the recipe serving size, determining a main food ingredient from the one or more food ingredients, and determining whether an amount of overlap of the main food ingredient in a receptacle of the cooking apparatus exceeds a predetermined threshold. If it is determined that the amount of overlap of the main food ingredient exceeds the predetermined threshold, then the scaled cooking time corresponding to the target serving size is determined based on the recipe scale factor and the recipe cooking time.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 10, 2025
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Yun Chen, Weishun Bao, Weimin Xiao
  • Patent number: 12327811
    Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: June 10, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
  • Patent number: 12325945
    Abstract: The present invention discloses an isolation type tunnel washer for cleaning clothes, which comprises a closed tunnel washer box body. A partition wall is provided in the middle of the tunnel washer box body, a feeding port and a discharging port are provided at two ends of the tunnel washer box body, and the feeding port and the discharging port are respectively located at two sides of the partition wall. A water vapor separation structure is mounted between the feeding port and the partition wall, the water vapor separation structure extracts and exhausts air from the interior of the tunnel washer box body, and a first door body and a second door body which can be opened and closed are respectively mounted at the feeding port and the discharging port.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: June 10, 2025
    Assignee: Jiangsu Sea-Lion Machinery Co., Ltd.
    Inventors: Shengang Cai, Weibing Lu, Lei Xia, Wenxian Tang, Zhiying Sun, Yun Chen, Jian Zhang, Sheng Guo, Xiuqing Cao
  • Publication number: 20250183094
    Abstract: Method for reducing the depth loading of dielectric structures on a substrate are disclosed. The substrate includes a set of isolated long dummy gate regions and a set of dense long dummy gate regions. Each dummy gate region is surrounded on each lateral side by a dielectric spacer and a continuous etch stop layer. A hard mask layer is formed over the substrate to exert a force that reduces stresses within the substrate. Each dummy gate is then etched to form an isolation volume and a trench in the substrate, and then filled with dielectric material to form a dielectric structure. The depth loading, or the difference in trench depths between the set of isolated long dielectric structures and the set of dense short dielectric structures, is thus reduced.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 5, 2025
    Inventors: Tzu-Ging Lin, Jun-Ye Liu, Chun-Liang Lai, Ai Hsuan Lee, Yun-Chen Wu
  • Publication number: 20250172141
    Abstract: A fixed scroll assembly, a scroll compressor, and a method for machining a fixed scroll assembly includes a fixed scroll component and a sealing assembly. The fixed scroll component includes an end plate, a fixed scroll roll extending from a first side of the end plate, and an enhanced vapor injection hole extending from an upper surface of the fixed scroll component to a compression cavity. The enhanced vapor injection hole has a first end leading to the compression cavity, and a second end leading to the exterior of the fixed scroll assembly. The sealing assembly is configured to seal the second end of the enhanced vapor injection hole; and part of the enhanced vapor injection hole comprises a recess formed in the fixed scroll roll.
    Type: Application
    Filed: June 30, 2023
    Publication date: May 29, 2025
    Applicant: Copeland Climate Technologies (Suzhou) Co., Ltd.
    Inventors: Xuan LIU, Yuancan FANG, Pei JIN, Lili LI, Bendong HE, Yun CHEN
  • Publication number: 20250172664
    Abstract: Disclosed are techniques for wireless communication. In an aspect, a first sensing node may obtain measurements of one or more paths of one or more first sensing reference signals associated with a second sensing node over a first wireless channel. The first sensing node may transmit, to a sensing entity, a first measurement report including a first channel target indicator (CTI) associated with the first wireless channel. In some cases, the first CTI indicates that the first wireless channel is estimated to include reflections from a target or that the first wireless channel is estimated to include clutter reflections absent target reflections.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 29, 2025
    Inventors: Marwen ZORGUI, Yun CHEN, Srinivas YERRAMALLI, Rajat PRAKASH
  • Publication number: 20250176232
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an isolation structure extending into a front-side surface of a substrate. The isolation structure laterally encloses a first device region of the substrate. The isolation structure comprises a pair of isolation edges elongated in a first direction and at least partially defining the first device region. A pair of source/drain regions is disposed within the first device region and laterally spaced from one another in the first direction. A first gate electrode structure is disposed in the first device region between the pair of source/drain regions. The first gate electrode structure comprises a first pair of opposing sidewalls elongated in the first direction. The opposing sidewalls are laterally offset from a corresponding isolation edge in the pair of isolation edges by a non-zero distance in a direction towards a center of the first gate electrode structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 29, 2025
    Inventors: Yi-Huan Chen, Yu-Chang Jong, Fei-Yun Chen, Chien-Chih Chou, Chia-Jui Lee
  • Patent number: 12310530
    Abstract: Provided is a system (100) for determining the main ingredients of a food recipe. The system comprises a first input (102) for receiving the identity and mass fraction (wri) of each ingredient (i) in the food recipe (r), and a second input (104) for receiving the identity of ingredients of each known recipe of a population of known recipes. The system further includes a controller (106) configured to calculate, for each ingredient (i), the fraction (P(i)) of the population which uses the ingredient. The controller then calculates, using the fraction (P(i)) and the mass fraction (wri), a value (Vri) which positively correlates with the mass fraction (wri) and negatively correlates with the fraction (P(i)). The main ingredients are then determined according to the ingredients which have values (Vri) equal to or greater than a threshold value.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 27, 2025
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Wei Shun Bao, Weimin Xiao, Yun Chen
  • Patent number: 12310990
    Abstract: The present disclosure provides a method for treating arthritis by using a stem cell preparation. The stem cell preparation of the present disclosure can effectively delay cartilage degeneration caused by arthritis, and it is confirmed by whole blood analysis and blood biochemical analysis that the stem cell preparation in the form of three-dimensional stem cell spheres provides a safe treatment for arthritis. The present disclosure also provides a method for preparing the stem cell preparation.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: May 27, 2025
    Assignee: GWO XI STEM CELL APPLIED TECHNOLOGY CO., LTD.
    Inventors: Feng-Huei Lin, Che-Yung Kuan, Yu-Ying Lin, Ching-Yun Chen, Zhi-Yu Chen, I-Hsuan Yang, Ming-Hsi Chuang, Po-Cheng Lin, Chia-Hsin Lee, Kai-Ling Zhang, Pei-Syuan Chao, Wan-Sin Syu, Chun-Hung Chen, Ting-Ju Wang
  • Patent number: 12315819
    Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Chen-Hua Yu, Hui-Jung Tsai
  • Publication number: 20250163260
    Abstract: A low-dielectric resin composition includes an epoxy resin, an active ester compound, a modified polyphenylene ether resin, and an inorganic filler material. Based on a total weight of the low-dielectric resin composition being 100 wt %, a content of the epoxy resin ranges from 5 wt % to 30 wt %, a content of the active ester compound ranges from 5 wt % to 40 wt %, a content of the modified polyphenylene ether resin ranges from 0.1 wt % to 20 wt %, and a content of the inorganic filler material is not less than 40 wt %. A ratio of the content of the active ester compound relative to the content of the epoxy resin ranges from 0.5 to 2.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 22, 2025
    Inventors: TE-CHAO LIAO, LI-YUN CHEN, WEI-RU HUANG, HUNG-YI CHANG, CHIA-LIN LIU
  • Patent number: D1083743
    Type: Grant
    Filed: April 16, 2025
    Date of Patent: July 15, 2025
    Inventors: Yun Chen, Xiaogang He