Patents by Inventor Yun Chen

Yun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978472
    Abstract: A system for processing and presenting a conversation includes a sensor, a processor, and a presenter. The sensor is configured to capture an audio-form conversation. The processor is configured to automatically transform the audio-form conversation into a transformed conversation. The transformed conversation includes a synchronized text, wherein the synchronized text is synchronized with the audio-form conversation. The presenter is configured to present the transformed conversation including the synchronized text and the audio-form conversation. The presenter is further configured to present the transformed conversation to be navigable, searchable, assignable, editable, and shareable.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: May 7, 2024
    Assignee: Otter.ai, Inc.
    Inventors: Yun Fu, Simon Lau, Kaisuke Nakajima, Julius Cheng, Gelei Chen, Sam Song Liang, James Mason Altreuter, Kean Kheong Chin, Zhenhao Ge, Hitesh Anand Gupta, Xiaoke Huang, James Francis McAteer, Brian Francis Williams, Tao Xing
  • Publication number: 20240145706
    Abstract: The present invention provides a core-shell cathode characterized by comprising: a shell comprising an electrically conductive, porous carbon material; and a core, which is an inner cavity enclosed within the shell, wherein the core contains an active material and an electrolyte, and the active material comprises liquid polysulfide having the general formula Li2Sx, wherein 4?x?8; the shell comprises a first layer, an O-ring and a second layer sequentially stacked from bottom to top to form the inner cavity to contain the active material and the electrolyte. The present invention also provides a lithium-sulfur battery using said core-shell cathode, which attains both high sulfur loading and high sulfur content, and simultaneously satisfies high energy density, high capacity retention and high cycle stability under lean-electrolyte condition.
    Type: Application
    Filed: December 23, 2022
    Publication date: May 2, 2024
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Sheng-Heng CHUNG, Yun-Chen WU
  • Publication number: 20240145431
    Abstract: A method includes: attaching a first die and a second die to a substrate, the first die comprising a conductive via; forming a die spacer between the first die and the second die; thinning the first die and the second die, wherein after thinning the first die and the second die, the die spacer protrudes a first height above an upper surface of the first die; depositing an insulating layer over the first die and the second die; planarizing the insulating layer, wherein after planarizing, the insulating layer has a first thickness above the first die and a second thickness above the die spacer; attaching a third die and a fourth die to the first die and the second die; and attaching a support substrate to the third die and the fourth die.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 2, 2024
    Inventors: Yung-Lung Chen, Ming-Yun Liao, Yi-Hsiu Chen, Wen-Chih Chiou
  • Publication number: 20240145244
    Abstract: A method of patterning an underlying structure includes the following. A first patterning process is performed on the underlying structure to form a first patterned underlying structure including a first opening. A patterned photoresist layer is formed, and the patterned photoresist layer fills the first opening. A second patterning process is performed on the first patterned underlying structure to form a second patterned underlying structure including the first opening and a second opening.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 2, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Yun-An Chen, Hsiao-Shan Huang, Hsiao-Chiang Lin
  • Patent number: 11969716
    Abstract: This application discloses a silicon carbide (SiC)-loaded graphene photocatalyst for hydrogen production under visible light irradiation and a preparation method thereof. Pure SiC and pure black carbon are respectively prepared and mixed to obtain a mixture with a resistance less than 100?. Then the mixture was vacuumized and processed with a current pulse with an increasing voltage until a breakdown occurs, and subjected to ultrasonic stirring, centrifugal washing and vacuum drying in turn to obtain the SiC-loaded graphene photocatalyst. By means of the current pulse, a heterojunction is formed between SiC and graphene to improve the catalytic activity of the photocatalyst; and the photocatalytic hydrogen production rate of SiC nanoparticles can be enhanced after loaded on the graphene.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: April 30, 2024
    Assignee: Guangdong University of Technology
    Inventors: Yun Chen, Shengbao Lai, Biao Li, Zuohui Liu, Guanhai Wen, Maoxiang Hou, Xin Chen
  • Patent number: 11969771
    Abstract: A method of fabricating a film vibration device, including: photoetching a surface of a silicon wafer to form a circular-hole array; etching an aluminum layer on the silicon wafer; etching the silicon wafer to form a through-hole array to obtain a porous silicon wafer; attaching a polyethylene terephthalate (PET) sheet to a side of the porous silicon wafer; ablating the PET sheet to obtain a porous PET film; attaching a polyvinylidene fluoride (PVDF) film to a lower side of the porous silicon wafer; performing vacuumization above the porous silicon wafer, while heating the PVDF film below the porous silicon wafer to create dome micro-structures on the PVDF film; and laminating the porous PET film on each of two sides of the PVDF film to obtain the film vibration device. This application also provides a cleaning device having the film vibration device.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: April 30, 2024
    Assignee: Guangdong University of Technology
    Inventors: Yun Chen, Biao Li, Aoke Song, Shankun Dong, Shengbao Lai, Maoxiang Hou, Xin Chen
  • Publication number: 20240136438
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 25, 2024
    Inventors: Yu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
  • Publication number: 20240133995
    Abstract: In an aspect, a method performed by a network node includes obtaining a first plurality of radio frequency fingerprint positioning (RFFP) measurements corresponding to a plurality of known displacements between positions of a user equipment (UE); and training a positioning model to provide a position estimate of the UE, wherein the training of the positioning model is at least based on the first plurality of RFFP measurements and the known displacements between the positions of the UE corresponding to the first plurality of RFFP measurements.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Mohammed Ali Mohammed HIRZALLAH, Srinivas YERRAMALLI, Yun CHEN, Rajat PRAKASH, Taesang YOO
  • Publication number: 20240131819
    Abstract: A thermally conductive board includes a first metal layer, a second metal layer, and a thermally conductive layer. The material of the first metal layer includes copper, and the first metal layer has a first top surface and a first bottom surface opposite to the first top surface. A first metal coating layer covers the first bottom surface. The material of the second metal layer includes copper, and the second metal layer has a second top surface and a second bottom surface opposite to the second top surface. A second metal coating layer covers the second top surface and faces the first metal coating layer. The thermally conductive layer is an electrically insulator laminated between the first metal coating layer and the second metal coating layer.
    Type: Application
    Filed: May 3, 2023
    Publication date: April 25, 2024
    Inventors: KAI-WEI LO, WEN-FENG LEE, HSIANG-YUN YANG, KUO-HSUN CHEN
  • Publication number: 20240133473
    Abstract: The application relates to an anti-back-transfer intake structure of a rotating detonation combustion chamber including a Tesla valve communicating with the rotating detonation combustion chamber and arranged at an inlet of the rotating detonation combustion chamber. The Tesla valve includes a casing and a flow passage, the casing is coaxially connected with an outer wall of the rotating detonation combustion chamber, the flow passage is arranged in the casing, and the flow passage has an inlet end for introducing air, and an outlet end connected with an annular passage of the rotating detonation combustion chamber.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Feilong SONG, Yun WU, Xin CHEN, Min JIA, Huimin SONG, Shanguang GUO, Zhao YANG, Jiaojiao WANG
  • Publication number: 20240132412
    Abstract: In one aspect, the present disclosure relates to doped thermoelectric oxide ceramic compositions comprising stable cerium oxide nanoinclusions. In a further aspect, the thermoelectric oxide ceramic compositions comprise calcium cobaltite ceramic with a dopant, such as bismuth. The disclosed doped thermoelectric ceramic oxide compositions comprising ceramic oxide nanoinclusions have reduced thermal conductivity and an increased energy conversion efficiency as compared to a conventional doped thermoelectric oxide ceramic material without cerium oxide nanoninclusions. Also disclosed herein are methods for making the doped thermoelectric ceramic oxide compositions.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 25, 2024
    Inventors: Xueyan SONG, Cesar-Octavio ROMO-DE-LA-CRUZ, Geoffroy GAUNEAU, Liang LIANG, Yun CHEN
  • Patent number: 11967667
    Abstract: A micro light-emitting diode structure is provided. The micro light-emitting diode structure includes an epitaxial layer. The micro light-emitting diode structure also includes a reflecting layer disposed on the epitaxial layer. The micro light-emitting diode structure further includes a patterned electrode layer disposed between the epitaxial layer and the reflecting layer. The patterned electrode layer is divided into a plurality of patterned electrode segments, and the patterned electrode segments are separated from each other. Moreover, the micro light-emitting diode structure includes a first-type electrode and a second-type electrode disposed on the reflecting layer and electrically connected to the epitaxial layer.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: April 23, 2024
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Chee-Yun Low, Fei-Hong Chen, Pai-Yang Tsai
  • Patent number: 11963450
    Abstract: A method for manufacturing a core-shell coaxial gallium nitride (GaN) piezoelectric nanogenerator is provided. A mask covering a center part of a gallium nitride wafer is removed. An electrodeless photoelectrochemical etching is performed on the gallium nitride wafer to form a primary GaN nanowire array on a surface of the gallium nitride wafer. A precious metal layer provided on the surface of the gallium nitride wafer is removed and an alumina layer is deposited on the surface of the gallium nitride wafer to cover the primary GaN nanowire array to obtain a core-shell coaxial GaN nanowire array. A first conductive layer is provided on a flexible substrate to which the core-shell coaxial GaN nanowire array is transferred. A second conductive layer is provided at a top end of the core-shell coaxial GaN nanowire array, and is connected to an external circuit to obtain the core-shell coaxial GaN piezoelectric nanogenerator.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: April 16, 2024
    Assignee: Guangdong University of Technology
    Inventors: Yun Chen, Pengfei Yu, Aoke Song, Zijian Li, Maoxiang Hou, Xin Chen
  • Publication number: 20240115079
    Abstract: A food preparation system weighs ingredients added to a receptacle. For identified ingredient and its added weight, a corresponding amount of a set of different sugar type is estimated, and a total sugar content and a sweetness index of the overall recipe is derived. The system determines if there are suitable alternative recipes with reduced total sugar content and similar sweetness index and suggests such determined alternative recipes to the user.
    Type: Application
    Filed: January 24, 2022
    Publication date: April 11, 2024
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Yun CHEN, Anna Louise WIJNOLTZ, Henriette Christine Marie HOONHOUT, Jasper DE VREEDE
  • Publication number: 20240120030
    Abstract: The present application provides a method for analyzing droplets on the basis of volume distribution including obtaining a total volume V of a sample containing target molecules based on a system prepared using the sample. The system is emulsified into droplets. A droplet system is obtained when the droplets obtaining the sample executes an amplification reaction. A droplet image of the droplet system is obtained. A total number n of droplets included in the droplet system is obtained based on the droplet image. A droplet volume distribution of the droplet system is obtained based on the droplet image. A number j of negative droplets among the n droplets is counted. A quantitative analysis is performed for the target molecules according to the total volume V of the sample, the total number n of droplets, the droplet volume distribution information, and the number j of negative droplets.
    Type: Application
    Filed: January 13, 2021
    Publication date: April 11, 2024
    Inventors: YUN XIA, XIA ZHAO, YANG XI, YI WEI, FANG CHEN, HUI JIANG
  • Publication number: 20240117329
    Abstract: Disclosed are a cocaine esterase mutant and use thereof. The cocaine esterase mutant is obtained by mutating a wildtype cocaine esterase, an amino acid sequence of the wildtype cocaine esterase is shown as SEQ ID No.1, the cocaine esterase mutant is T172R/G173Q/L196C/I301C, or additionally added with V116K point mutation, or additionally added with A51 site mutation, and the A51 site mutation is L, Y, V, F or W. Catalytic efficiency of the cocaine esterase mutant screened on a cocaine toxic metabolite benzoylecgonine is greatly improved compared with that of a wildtype enzyme.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 11, 2024
    Inventors: Xiabin CHEN, Jianzhuang YAO, Shurong HOU, Xingyu DENG, Yun ZHANG, Junsen TONG
  • Publication number: 20240119912
    Abstract: The present disclosure provides a driving method for a liquid crystal display panel and a non-transitory computer storage medium. The driving method includes: for the plurality of sub-pixels, adopting a first gray-level table for displaying a picture in other frame pictures other than a first frame picture in each of the plurality of predetermined periods, the first gray-level table including a plurality of first gray-level values; and adopting a second gray-level table for displaying a picture in the first frame picture in each of the plurality of predetermined periods, the second gray-level table including a plurality of second gray-level values.
    Type: Application
    Filed: March 22, 2021
    Publication date: April 11, 2024
    Inventors: Hangyu CHEN, Lijun XIAO, Junmin ZHANG, Bing LI, Feng JIANG, Meng FENG, Mengchao SHUAI, Jianmin XIANG, Yun BAI
  • Patent number: 11956917
    Abstract: A tray module is applicable to a chassis. The chassis includes at least two side plates. Each side plate has a guiding portion. The guiding portion includes a first horizontal section and an ascending section, and the ascending section is connected to the first horizontal section. The tray module includes a carrier body, at least two first connecting rods, and at least two second connecting rods. Each first connecting rod has a movable end and a driven end. The movable end is pivotally connected to the carrier body and slidably disposed in the guiding portions. Each second connecting rod has a pivotal end, a pivotal connection portion, and an operating end. The pivotal connection portion is located between the pivotal end and the operating end. Each pivotal end is pivotally connected to the each side plate. Each driven end is pivotally connected to each pivotal connection portion.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 9, 2024
    Assignee: WISTRON CORPORATION
    Inventors: Si-Yun Tan, Yi-Sheng Chen
  • Publication number: 20240113166
    Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ging Lin, Chun-Liang Lai, Yun-Chen Wu, Ya-Yi Tsai, Shu-Yuan Ku, Shun-Hui Yang
  • Publication number: 20240113187
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong, Chi-Te Lin