Patents by Inventor Yun Cheng

Yun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200145658
    Abstract: A post processing apparatus includes a super-resolution (SR) filtering circuit and a loop restoration (LR) filtering circuit. The SR filtering circuit applies SR filtering to a processing result of a preceding circuit. The LR filtering circuit applies LR filtering to a processing result of the SR filtering circuit. Before the SR filtering circuit finishes SR filtering of all pixels of a frame that are generated by the preceding circuit, the LR filtering circuit starts LR filtering of pixels that are derived from applying SR filtering to pixels included in the frame.
    Type: Application
    Filed: October 28, 2019
    Publication date: May 7, 2020
    Inventors: Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Chi-Hung Chen, Kai-Chun Lin, Chih-Wen Yang, Hsuan-Wen Peng
  • Publication number: 20200135589
    Abstract: A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 30, 2020
    Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
  • Publication number: 20200117848
    Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
  • Publication number: 20200101582
    Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.
    Type: Application
    Filed: January 18, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Wen Liu, Hao-Yun Cheng, Che-Hao Tu, Kei-Wei Chen
  • Publication number: 20200106048
    Abstract: The present disclosure relates to a display panel, a manufacturing method thereof, and a display terminal. The display panel includes an interlayer insulating layer, a planarization layer, and a pixel defining layer stacked in sequence. The display panel further includes a sub-pixel, a cathode, and a thin film encapsulation structure. The pixel defining layer is provided with an opening. The sub-pixel is disposed in the opening of the pixel defining layer, and the cathode is disposed on the pixel defining layer and covers the sub-pixel. The thin film encapsulation structure is disposed on the cathode, and the thin film encapsulation structure or the cathode is provided with a first embedded portion. The first embedded portion is embedded in the pixel defining layer and the planarization layer, and is in contact with the interlayer insulating layer.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Inventors: Peng XU, Yun CHENG, Lufangyue JI, Tongkai ZHOU, Wei DU, Gang CEN
  • Patent number: 10515185
    Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
  • Publication number: 20190378961
    Abstract: A flip-chip light-emitting module includes a thermal dissipation substrate, a package assembly, and a light-emitting chip. The package assembly includes a frame surrounding the thermal dissipation substrate, and a lens unit disposed on the frame. The frame includes a conductive path. The light-emitting chip is disposed on the thermal dissipation substrate, and includes a top conductive contact and a light-emitting surface at the same side. The top conductive contact is electrically connected with the conductive path by a conductor.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 12, 2019
    Inventors: KUNG-AN LIN, CHUNG-CHE YANG, HUNG-WEI LIN, HSIANG-YUN CHENG
  • Patent number: 10473981
    Abstract: A display device includes a backlight module, a liquid crystal layer, a lower polarizer, an upper polarizer, and a retardation layer. The liquid crystal layer is disposed on a lighting side of the backlight module while the lower polarizer is disposed between the liquid crystal layer and the backlight module. The upper polarizer is disposed on a side of the liquid crystal layer opposite to the lower polarizer, and the retardation layer is between the upper and lower polarizers. The retardation layer has a retardation area that may modulates the light passing through the lower polarizer and make the light passes through the upper polarizer.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 12, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Wang-Shuo Kao, Wen-Fang Sung, Zhi-Lu Ye, Yun Cheng
  • Patent number: 10433655
    Abstract: A positioning device for a supporting cloth has two first connecting rods and two second connecting rods. The two first connecting rods are respectively disposed on a frame. Each one of the two first connecting rods has two supporting portions formed on two ends of the first connecting rod. The second connecting rods are respectively disposed on the frame and are both adjustably connected to the two first connecting rods to form a ring-like member. A distance between the two second connecting rods is adjustable. Each one of the second connecting rods has two protruding portions respectively formed on the two ends of the connecting rod. The two protruding portions are each inserted into a respective supporting portion. The positioning device is applied to be disposed on the frame for fixing a supporting cloth easily and increasing an elastic support effect of the supporting cloth.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 8, 2019
    Inventor: Yun-Cheng Hsiao
  • Publication number: 20190289320
    Abstract: In order to overcome the issue caused by a decoded block vector (BV) pointing to a reference block overlapping with an unavailable area, various methods are disclosed. According to one method, if the reference block overlaps with an unavailable area, the reference pixels in the unavailable area are generated for IntraBC prediction of the current block by padding from neighbouring available pixels. The padding can be done in the horizontal direction and then the vertical direction. The padding may also done in the vertical direction first and then horizontal direction. In another method, if the reference block overlaps with an unavailable area, the reference pixels in the unavailable area are generated for IntraBC prediction of the current block by using previous decoded pixels in the unavailable area. A pre-defined value may also be used for the unavailable area.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Applicant: MEDIATEK INC.
    Inventors: Tzu-Der CHUANG, Chia-Yun CHENG, Han-Liang CHOU, Ching-Yeh CHEN, Yu-Chen SUN, Yu-Wen HUANG
  • Publication number: 20190288067
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, a fin over the substrate and the isolation structure, a gate structure engaging a first portion of the fin, first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin, source/drain (S/D) features adjacent to the first sidewall spacers, and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers and the second portion of the fin include a same dopant.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 19, 2019
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Publication number: 20190281312
    Abstract: A palette decoding apparatus includes a palette color storage device which stores palette colors, a color index storage device which stores color indices of pixels, and a palette value processing circuit which generates a palette value for each pixel by reading data from the color index storage device and the palette color storage device. A frame is divided into first coding units, and each first coding unit is sub-divided into one or more second coding units. Before a palette value of a last pixel in a first coding unit is generated by the palette value processing circuit, a palette value of a non-last pixel in the first coding unit is generated by the palette value processing circuit and used by a reconstruction circuit of the video decoder.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Inventors: Chi-Min Chen, Min-Hao Chiu, Chia-Yun Cheng, Yung-Chang Chang
  • Patent number: 10412390
    Abstract: A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: September 10, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ming-Long Wu, Tung-Hsing Wu, Li-Heng Chen, Ting-An Lin, Yi-Hsin Huang, Chung-Hua Tsai, Chia-Yun Cheng, Han-Liang Chou, Yung-Chang Chang
  • Patent number: 10396156
    Abstract: A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Patent number: 10397588
    Abstract: A method and apparatus of sharing an on-chip buffer or cache memory for a video coding system using coding modes including Inter prediction mode or Intra Block Copy (IntraBC) mode are disclosed. At least partial pre-deblocking reconstructed video data of a current picture is stored in an on-chip buffer or cache memory. If the current block is coded using IntraBC mode, the pre-deblocking reconstructed video data of the current picture stored in the on-chip buffer or cache memory are used to derive IntraBC prediction for the current block. In some embodiments, if the current block is coded using Inter prediction mode, Inter reference video data from the previous picture stored in the on-chip buffer or cache memory are used to derive Inter prediction for the current block. In another embodiment, the motion compensation/motion estimation unit is shared by the two modes.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 27, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Der Chuang, Ping Chao, Ching-Yeh Chen, Yu-Chen Sun, Chih-Ming Wang, Chia-Yun Cheng, Han-Liang Chou, Yu-Wen Huang
  • Patent number: 10390028
    Abstract: Methods of palette coding to reduce the required coding process are disclosed. According to one method, smaller blocks are derived from a large block. The histogram of the large block is derived based on the histograms of smaller blocks in the large block. According to another method, one or more palette tables are derived based on multiple blocks. One palette table is used for each of the multiple blocks. According to yet another method, index map transpose is performed in the parsing stage according to the transpose flag of the index map. Accordingly, a buffer to store the transpose flags can be saved. According to still yet another method, the palette predictor update is performed using an index mapping table to avoid the need for shuffling the contents of the palette predictor stored in a palette buffer.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 20, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yu-Chen Sun, Tzu-Der Chuang, Han-Liang Chou, Chia-Yun Cheng, Ching-Yeh Chen, Yu-Wen Huang
  • Patent number: 10375395
    Abstract: A video processing apparatus includes an external storage device, a hardware entropy engine, and a software execution engine. The hardware entropy engine performs entropy processing of a current picture, and further outputs count information to the external storage device during the entropy processing of the current picture. When loaded and executed by the software execution engine, a software program instructs the software execution engine to convert the count information into count table contents, and generate a count table in the external storage device according to at least the count table contents. The count table is referenced to apply a backward adaptation to a probability table that is selectively used by the hardware entropy engine to perform entropy processing of a next picture.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 6, 2019
    Assignee: MEDIATEK INC.
    Inventors: Sheng-Jen Wang, Yung-Chang Chang, Chia-Yun Cheng
  • Publication number: 20190237543
    Abstract: A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Patent number: 10356438
    Abstract: In order to overcome the issue caused by a decoded block vector (BV) pointing to a reference block overlapping with an unavailable area, various methods are disclosed. According to one method, if the reference block overlaps with an unavailable area, the reference pixels in the unavailable area are generated for IntraBC prediction of the current block by padding from neighboring available pixels. The padding can be done in the horizontal direction and then the vertical direction. The padding may also done in the vertical direction first and then horizontal direction. In another method, if the reference block overlaps with an unavailable area, the reference pixels in the unavailable area are generated for IntraBC prediction of the current block by using previous decoded pixels in the unavailable area. A pre-defined value may also be used for the unavailable area.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 16, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Der Chuang, Chia-Yun Cheng, Han-Liang Chou, Ching-Yeh Chen, Yu-Chen Sun, Yu-Wen Huang
  • Publication number: 20190197598
    Abstract: A interactive product recommendation method is provided, including: selecting a target product from the plurality of products; loading the product information of the target product; generating a product list according to the product characteristics corresponding to the target product and the user preferences corresponding to at least one user, where the product list includes a plurality of icons corresponding to different products; generating a first label list based on at least one product characteristics corresponding to the target product and the user preferences corresponding to the user, where the first label list has a plurality of first labels corresponding to different product features; and displaying the product information, the product list and the first label list in a user interface. When clicking the icon, displaying another user interface corresponding to the clicked icon. When clicking the first label, updating the product list according to the clicked first label.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Chien-Yang GUO, Yun-Cheng CHOU, Chin-Sheng YEH, Chih-Pin SU, Shin-Yi WU