Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. A method of manufacturing a semiconductor device may include forming a stacked body in which first and second material layers are alternately stacked, the stacked body being formed in a chip area and a guard area, wherein the guard area is adjacent to the chip area, forming a plurality of first openings that pass through the stacked body of the guard area, the first openings being spaced apart from each other, forming a second opening from the plurality of first openings by expanding each of the plurality of first openings so that the plurality of first openings are coupled to each other, and forming a chip guard by filling the second opening with an insulating material.

Abstract: A semiconductor device may include a first gate structure including stacked first selection lines, each first selection line including a first cell region and a first pad region adjacent in a first direction, a second gate structure including stacked second selection lines, each second selection line including a second cell region and a second pad region adjacent in the first direction, first contact plugs extending through the first pad region and respectively connected to the first selection lines, and second contact plugs extending through the second pad region and respectively connected to the second selection lines, and in a second direction crossing the first direction, the first pad region may have a width greater than that of the first cell region, and the second pad region may have a width greater than that of the first pad region.

Abstract: Provided herein is a method of manufacturing a memory device. The method may include forming an ion implantation region in a portion of an outer portion of an underlying structure by implanting ions into the underlying structure, transforming the ion implantation region into an etch stop pattern, forming a target structure on the underlying structure including the etch stop pattern, and performing an etching process to form first holes and second holes in the target structure, wherein the first width of the first holes is different than the second width of the second holes. The etching process is performed until the etch stop pattern is exposed through the first holes and the second holes.

Abstract: A semiconductor device may include: a gate structure including insulating layers and control gates, which are alternately stacked; a channel layer penetrating the gate structure; floating gates respectively located between the control gates and the channel layer; first blocking patterns respectively located between the control gates and the floating gates; and a second blocking pattern located between the first blocking patterns and the control gates and between the control gates and the insulating layers, the second blocking pattern including a material with a dielectric constant that is higher than that of the first blocking patterns.

Abstract: A semiconductor device may include a stack including a chip region and a guard region surrounding the chip region, contact structures positioned in the chip region, and a chip guard structure positioned in the guard region and including first protrusions protruding by a first width and second protrusions protruding by a second width greater than the first width.

Abstract: A semiconductor device may include: a first gate structure in a first memory block and including stacked first gate lines, the first gate lines extending from a plane center region to a plane edge region; a second gate structure in a second memory block adjacent to the first memory block and including stacked second gate lines, the second gate lines extending from the plane center region to the plane edge region; an isolation insulating structure located a) between the first gate structure and the second gate structure in the plane edge region, the isolation insulating structure including stacked insulating plates and insulating pillars extending through the insulating plates; and a slit structure located a) between the first gate structure and the second gate structure and b) in the plane center region, the slit structure connected to the isolation insulating structure, and including irregularities on a sidewall thereof.

Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a stack structure including a cell array region and a contact region extending from the cell array region, a cell plug penetrating the cell array region of the stack structure, a conductive gate contact penetrating the contact region of the stack structure, and a plurality of first support structures bordering a perimeter of the conductive gate contact and disposed to be spaced apart from the center of the conductive gate contact at a first distance.

Abstract: A semiconductor device may include a gate structure including insulating layers and conductive layers that are alternately stacked, a real channel structure extending through the gate structure, a slit structure extending in a first direction along the sidewall of the gate structure, a contact structure extending through the gate structure and that is electrically connected to at least one conductive layer, among the conductive layers, and a pair of first supports extending in an arc form along the sidewall of the contact structure and that includes concave and convex parts on sidewalls of the first supports.

Abstract: A semiconductor device may include: a first gate structure; a second gate structure; an isolation insulation structure configured to extend in a first direction between the first gate structure and the second gate structure, and to have a first width in a second direction intersecting the first direction; and a first support located between the first gate structure and the second gate structure, and configured to have a second width greater than the first width in the second direction. The isolation insulation structure may protrude into the first support.

Abstract: A memory device includes isolation layers and gate structures alternately stacked on a lower structure and a tunnel isolation layer penetrating the isolation layers and the gate structures. The memory device also includes a channel layer formed along an inner wall of the tunnel isolation layer and a core plug formed along an inner wall of the channel layer. Each of the gate structures includes: a floating gate surrounding an outer wall of the tunnel isolation layer; a first dielectric layer surrounding an outer wall of the floating gate; a second dielectric layer surrounding an outer wall of the first dielectric layer; a third dielectric layer surrounding an outer wall of the second dielectric layer; and a gate line formed between the isolation layers, the gate line filling a region surrounded at least in part by the third dielectric layer.

Abstract: The present disclosure relates to a memory device including a first memory block including a first group of cell plugs and a second group of cell plugs, a second memory block including a third group of cell plugs and a fourth group of cell plugs, a connection region located between the first and second memory blocks, a first source select line commonly coupled to the first group of cell plugs and third group of cell plugs, a second source select line coupled to the second group of cell plugs, and a third source select line coupled to the fourth group of cell plugs.

Abstract: A semiconductor device may include: a gate structure including insulating layers and control gates, which are alternately stacked; a channel layer penetrating the gate structure; floating gates respectively located between the control gates and the channel layer; first blocking patterns respectively located between the control gates and the floating gates; and a second blocking pattern located between the first blocking patterns and the control gates and between the control gates and the insulating layers, the second blocking pattern including a material with a dielectric constant that is higher than that of the first blocking patterns.

Abstract: A photoplethysmography sensor is provided.

Abstract: An ECG sensor chip used in a wearable appliance includes; a switch controlled —by a switching signal, an amplifier that amplifies a difference between first and second ECG signals, and a location indicator that generates the switching signal. The switch passes either a first ECG signal or second ECG signal in response to the switching signal.

Abstract: An ECG sensor chip used in a wearable appliance includes; a switch controlled by a switching signal, an amplifier that amplifies a difference between first and second ECG signals, and a location indicator that generates the switching signal. The switch passes either a first ECG signal or second ECG signal in response to the switching signal.

Abstract: An ECG sensor chip used in a wearable appliance includes; a switch controlled by a switching signal, an amplifier that amplifies a difference between first and second ECG signals, and a location indicator that generates the switching signal. The switch passes either a first ECG signal or second ECG signal in response to the switching signal.

Abstract: A wearable patch-type automatic defibrillator attachable to a region of a patient near the patient's heart includes a battery which stores electrical energy for defibrillation, a controller which controls the battery, electrocardiogram (ECG) electrodes, and defibrillation electrodes. The controller analyzes ECG signals of the patient received through the ECG electrodes, and automatically provides the patient with the electrical energy stored in the battery through the defibrillation electrodes when defibrillation is needed according to a result of the analysis.

Abstract: An ECG sensor chip used in a wearable appliance includes; a switch controlled by a switching signal, an amplifier that amplifies a difference between first and second ECG signals, and a location indicator that generates the switching signal. The switch passes either a first ECG signal or second ECG signal in response to the switching signal.

Abstract: A regulator circuit includes an OP-amp, buffer, power transistor, voltage divider, load, and feedback current generator. The OP-amp generates first voltage signal by amplifying a difference between an input voltage signal and a feedback voltage signal. The OP-amp drives a first node as the first voltage signal. The buffer drives a second node as a second voltage signal generated based on the first voltage signal. The power transistor includes a drain terminal receiving a supply voltage, a gate terminal connected to the second node, and a source terminal connected to a third node. The voltage divider generates the feedback voltage signal by dividing an output voltage signal of the third node. The load includes a terminal connected to the third node and another terminal receiving a ground voltage. The feedback current generator provides a first feedback current corresponding to a ripple of the output voltage signal to the first node for enhancing a speed at which the ripple reduced.

Abstract: A method for broadcasting sports includes receiving a first bio-signal output from a first sensor attached to a first sports participant of a sporting event through a first wireless communications module, receiving a second bio-signal output from a second sensor attached to a second sports participant of the sporting event through a second wireless communications module, receiving live video data of the first sports participant and the second sports participant through cameras, and generating sports data including at least one of the first bio-signal and the second bio-signal and the live video data.