Abstract: A regulator circuit includes an OP-amp, buffer, power transistor, voltage divider, load, and feedback current generator. The OP-amp generates first voltage signal by amplifying a difference between an input voltage signal and a feedback voltage signal. The OP-amp drives a first node as the first voltage signal. The buffer drives a second node as a second voltage signal generated based on the first voltage signal. The power transistor includes a drain terminal receiving a supply voltage, a gate terminal connected to the second node, and a source terminal connected to a third node. The voltage divider generates the feedback voltage signal by dividing an output voltage signal of the third node. The load includes a terminal connected to the third node and another terminal receiving a ground voltage. The feedback current generator provides a first feedback current corresponding to a ripple of the output voltage signal to the first node for enhancing a speed at which the ripple reduced.

Abstract: An ECG sensor chip used in a wearable appliance includes; a switch controlled by a switching signal, an amplifier that amplifies a difference between first and second ECG signals, and a location indicator that generates the switching signal. The switch passes either a first ECG signal or second ECG signal in response to the switching signal.

Abstract: A method for broadcasting sports includes receiving a first bio-signal output from a first sensor attached to a first sports participant of a sporting event through a first wireless communications module, receiving a second bio-signal output from a second sensor attached to a second sports participant of the sporting event through a second wireless communications module, receiving live video data of the first sports participant and the second sports participant through cameras, and generating sports data including at least one of the first bio-signal and the second bio-signal and the live video data.

Abstract: A wearable patch-type automatic defibrillator attachable to a region of a patient near the patient's heart includes a battery which stores electrical energy for defibrillation, a controller which controls the battery, electrocardiogram (ECG) electrodes, and defibrillation electrodes. The controller analyzes ECG signals of the patient received through the ECG electrodes, and automatically provides the patient with the electrical energy stored in the battery through the defibrillation electrodes when defibrillation is needed according to a result of the analysis.

Abstract: An electrocardiogram (ECG) sensor includes an analog front end device configured to remove a DC offset in a first ECG signal received from a measuring electrode, and adjust a gain amplification value based on the first ECG signal. The analog front end device is configured to output an adjusted first ECG signal, the adjusted first ECG signal being based on the adjusted gain amplification value and the removed DC offset in the first ECG signal. The ECG sensor includes a digital signal processor configured to analyze and process the adjusted first ECG signal based on an algorithm and to output information. The analog front end device is configured to remove the DC offset in the first ECG signal during a first period, and remove a DC offset in a second ECG signal and simultaneously adjust a gain amplification value for the second ECG signal during a second period.

Abstract: A system and method that generate a vibration motor driving signal includes; a first control unit that receives a first input signal and gain-adjusts the first input signal in response to a reference voltage to generate a first output signal, and a second control unit that receives the first output signal and gain-adjusts the first output signal in response to the reference voltage to generate a second output signal, wherein the second output signal is applied to a vibration motor as the vibration control signal.

Abstract: An electrocardiogram (ECG) sensor includes an analog front end device configured to remove a DC offset in a first ECG signal received from a measuring electrode, and adjust a gain amplification value based on the first ECG signal. The analog front end device is configured to output an adjusted first ECG signal, the adjusted first ECG signal being based on the adjusted gain amplification value and the removed DC offset in the first ECG signal. The ECG sensor includes a digital signal processor configured to analyze and process the adjusted first ECG signal based on an algorithm and to output information. The analog front end device is configured to remove the DC offset in the first ECG signal during a first period, and remove a DC offset in a second ECG signal and simultaneously adjust a gain amplification value for the second ECG signal during a second period.

Abstract: A method of calibrating the frequency of a gm-C filter is provided. The method includes generating, by a frequency calibration circuit, a calibration code capable of tuning a cut-off frequency of the gm-C filter according to a frequency of an oscillation signal that is output from a gm-C oscillator and indicates a process distribution and a reference code, determining, by the frequency calibration circuit, whether the calibration code exists within a range of a reference code, and outputting, by the frequency calibration circuit, the calibration code to the gm-C filter or generating a variable current to simultaneously tune transconductance of the gm-C oscillator and transconductance of the gm-C filter, according to a result of the determination.

Abstract: A system and method that generate a vibration motor driving signal includes; a first control unit that receives a first input signal and gain-adjusts the first input signal in response to a reference voltage to generate a first output signal, and a second control unit that receives the first output signal and gain-adjusts the first output signal in response to the reference voltage to generate a second output signal, wherein the second output signal is applied to a vibration motor as the vibration control signal.

Abstract: A method of calibrating the frequency of a gm-C filter is provided. The method includes generating, by a frequency calibration circuit, a calibration code capable of tuning a cut-off frequency of the gm-C filter according to a frequency of an oscillation signal that is output from a gm-C oscillator and indicates a process distribution and a reference code, determining, by the frequency calibration circuit, whether the calibration code exists within a range of a reference code, and outputting, by the frequency calibration circuit, the calibration code to the gm-C filter or generating a variable current to simultaneously tune transconductance of the gm-C oscillator and transconductance of the gm-C filter, according to a result of the determination.

Abstract: An equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay may improve group delay characteristics in the equalizer. The equalizer circuit may include a first low pass filter configured to filter a received input signal to output a filtered input signal, and a gain control circuit connected to an output terminal of the first low pass filter, and configured to modulate a gain of a transfer function for the equalizer. The equalizer may include a group delay compensation circuit connected to the output terminal of the first low pass filter and configured to compensate for a group delay of the input signal, and a second low pass filter connected to the output terminal of the first low pass filter.

Abstract: Provided is a filter used for an equalizer, the filter including: a first low-pass filter unit receives an input signal and performs low frequency band filtering on the input signal; and an equalization unit that receives an output signal from the first low-pass filter unit. The equalization unit may comprise a plurality of serially connected biquad low-pass filter units, and may control a value of a capacitor that is used to control a group delay value that is generated during equalization. Thus, the filter can compensate for group delay without including a separate all pass filter, thereby reducing surface area and power consumption.

Abstract: Provided is a filter used for an equalizer, the filter including: a first low-pass filter unit receives an input signal and performs low frequency band filtering on the input signal; and an equalization unit that receives an output signal from the first low-pass filter unit. The equalization unit may comprise a plurality of serially connected biquad low-pass filter units, and may control a value of a capacitor that is used to control a group delay value that is generated during equalization. Thus, the filter can compensate for group delay without including a separate all pass filter, thereby reducing surface area and power consumption.

Abstract: An equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay may improve group delay characteristics in the equalizer. The equalizer circuit may include a first low pass filter configured to filter a received input signal to output a filtered input signal, and a gain control circuit connected to an output terminal of the first low pass filter, and configured to modulate a gain of a transfer function for the equalizer. The equalizer may include a group delay compensation circuit connected to the output terminal of the first low pass filter and configured to compensate for a group delay of the input signal, and a second low pass filter connected to the output terminal of the first low pass filter.

Abstract: Provided are a frequency synthesizer and a frequency synthesizing method. The frequency synthesizer includes a ring oscillator, duty buffers, half adders, and a switch. The ring oscillator receives a pair of input signals and generates a pair of oscillating signals. The duty buffers receive the pair of oscillating signals of the ring oscillator and generates output signals with predetermined duty cycles. The half adders receive output signals of the duty buffers and generate an output signal as a result of an Exclusive-OR operation on the output signals of the duty buffers and an output signal as a result of an AND operation on the output signals of the duty buffers. The switch selects one of the oscillating signals of the ring oscillator, the output signals as results of the Exclusive-OR operation, and the output signals as results of the AND operation.

Abstract: Provided are a frequency synthesizer and a frequency synthesizing method. The frequency synthesizer includes a ring oscillator, duty buffers, half adders, and a switch. The ring oscillator receives a pair of input signals and generates a pair of oscillating signals. The duty buffers receive the pair of oscillating signals of the ring oscillator and generates output signals with predetermined duty cycles. The half adders receive output signals of the duty buffers and generate an output signal as a result of an Exclusive-OR operation on the output signals of the duty buffers and an output signal as a result of an AND operation on the output signals of the duty buffers. The switch selects one of the oscillating signals of the ring oscillator, the output signals as results of the Exclusive-OR operation, and the output signals as results of the AND operation.