Patents by Inventor Yun-Cheol Han

Yun-Cheol Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7733166
    Abstract: Provided is a filter used for an equalizer, the filter including: a first low-pass filter unit receives an input signal and performs low frequency band filtering on the input signal; and an equalization unit that receives an output signal from the first low-pass filter unit. The equalization unit may comprise a plurality of serially connected biquad low-pass filter units, and may control a value of a capacitor that is used to control a group delay value that is generated during equalization. Thus, the filter can compensate for group delay without including a separate all pass filter, thereby reducing surface area and power consumption.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yun-Cheol Han
  • Publication number: 20090072896
    Abstract: Provided is a filter used for an equalizer, the filter including: a first low-pass filter unit receives an input signal and performs low frequency band filtering on the input signal; and an equalization unit that receives an output signal from the first low-pass filter unit. The equalization unit may comprise a plurality of serially connected biquad low-pass filter units, and may control a value of a capacitor that is used to control a group delay value that is generated during equalization. Thus, the filter can compensate for group delay without including a separate all pass filter, thereby reducing surface area and power consumption.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 19, 2009
    Inventor: Yun-Cheol Han
  • Publication number: 20050174189
    Abstract: An equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay may improve group delay characteristics in the equalizer. The equalizer circuit may include a first low pass filter configured to filter a received input signal to output a filtered input signal, and a gain control circuit connected to an output terminal of the first low pass filter, and configured to modulate a gain of a transfer function for the equalizer. The equalizer may include a group delay compensation circuit connected to the output terminal of the first low pass filter and configured to compensate for a group delay of the input signal, and a second low pass filter connected to the output terminal of the first low pass filter.
    Type: Application
    Filed: January 27, 2005
    Publication date: August 11, 2005
    Inventors: Woo-Kang Jin, Yun-Cheol Han
  • Patent number: 6917224
    Abstract: Provided are a frequency synthesizer and a frequency synthesizing method. The frequency synthesizer includes a ring oscillator, duty buffers, half adders, and a switch. The ring oscillator receives a pair of input signals and generates a pair of oscillating signals. The duty buffers receive the pair of oscillating signals of the ring oscillator and generates output signals with predetermined duty cycles. The half adders receive output signals of the duty buffers and generate an output signal as a result of an Exclusive-OR operation on the output signals of the duty buffers and an output signal as a result of an AND operation on the output signals of the duty buffers. The switch selects one of the oscillating signals of the ring oscillator, the output signals as results of the Exclusive-OR operation, and the output signals as results of the AND operation.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: July 12, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yun-Cheol Han
  • Publication number: 20040212403
    Abstract: Provided are a frequency synthesizer and a frequency synthesizing method. The frequency synthesizer includes a ring oscillator, duty buffers, half adders, and a switch. The ring oscillator receives a pair of input signals and generates a pair of oscillating signals. The duty buffers receive the pair of oscillating signals of the ring oscillator and generates output signals with predetermined duty cycles. The half adders receive output signals of the duty buffers and generate an output signal as a result of an Exclusive-OR operation on the output signals of the duty buffers and an output signal as a result of an AND operation on the output signals of the duty buffers. The switch selects one of the oscillating signals of the ring oscillator, the output signals as results of the Exclusive-OR operation, and the output signals as results of the AND operation.
    Type: Application
    Filed: January 23, 2004
    Publication date: October 28, 2004
    Inventor: Yun Cheol Han