Patents by Inventor Yun Chung

Yun Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134387
    Abstract: Flight control systems, flight control laws, and aircraft are provided. An flight control system includes an input configured to receive a pitch rate command, a processor operative to receive the pitch angle command, to calculate a pitch angle saturation limit, to compare the sum of the pitch rate command, the scaled pitch rate, and the scaled pitch angle to the pitch angle saturation limit, to convert the pitch rate command system to the pitch angle command system in response to the sum exceeding the pitch angle saturation limit value to limit the pilot pitch-up pitch rate command, and to couple the pitch rate command to an aircraft control surface for the failure case of one of control surface, and the aircraft control surface configured to adjust an aircraft control surface setting in response to the pitch rate command and/or pitch angle command to protect an aircraft from being in stall condition.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 25, 2024
    Applicant: Gulfstream Aerospace Corporation
    Inventors: Jong-Yeob Shin, Gi-Yun Chung, Lakmal Kaviratna
  • Publication number: 20240134136
    Abstract: An optical transceiver module temperature control device includes a processor, a printed circuit board assembly, an optical transceiver module and a temperature adjustment element. The processor is configured to measure an ambient temperature. The printed circuit board assembly includes a first side and a second side. The first side is opposite to the second side. The optical transceiver module is disposed on the first side of the printed circuit board assembly. The temperature adjustment element is coupled to the processor and disposed on the second side of the printed circuit board assembly. The processor is configured to generate a temperature adjustment signal according to the ambient temperature and an operating temperature range. The temperature adjustment element is configured to perform heat exchange with the printed circuit board assembly according to the temperature adjustment signal to adjust a temperature of the optical transceiver module into the operating temperature range.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Formerica Optoelectronics, Inc.
    Inventors: Yun-Cheng HUANG, Yi-Nan SHIH, Chih-Chung LIN, Yun-Chin TSAI
  • Patent number: 11966077
    Abstract: A light emission apparatus includes a laser diode configured to emit a light; a laser driver electrically coupled to the laser diode, the laser driver being configured to drive the laser diode to generate the light; and an optical module arranged to receive the light emitted by the laser diode, the optical module comprising at least one optical element and being configured to adjust the light and emits a transmitting light; wherein the transmitting light emits from the optical module with an illumination angle and the optical module adjusts the light to vary the illumination angle.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 23, 2024
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Chien-Lung Chen, Chieh-Ting Lin, Yu-Yi Hsu, Hui-Wen Chen, Bo-Jiun Chen, Shih-Tai Chuang
  • Publication number: 20240128194
    Abstract: Integrated circuit packages and methods of forming the same are provided. In an embodiment, a device includes: a power distribution interposer including: a first bonding layer; a first die connector in the first bonding layer; and a back-side interconnect structure including a power rail connected to the first die connector; and an integrated circuit die including: a second bonding layer directly bonded to the first bonding layer by dielectric-to-dielectric bonds; a second die connector in the second bonding layer, the second die connector directly bonded to the first die connector by metal-to-metal bonds; and a device layer on the second bonding layer, the device layer including a contact and a transistor, the transistor including a first source/drain region, the contact connecting a back-side of the first source/drain region to the second die connector.
    Type: Application
    Filed: January 9, 2023
    Publication date: April 18, 2024
    Inventors: Ming-Fa Chen, Yun-Han Lee, Lee-Chung Lu
  • Publication number: 20240128231
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 18, 2024
    Inventors: Fu Wei Liu, Pei-Wei Lee, Yun-Chung Wu, Bo-Yu Chiu, Szu-Hsien Lee, Mirng-Ji Lii
  • Publication number: 20240124298
    Abstract: Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 18, 2024
    Inventors: Yun-Chung Wu, Jhao-Yi Wang, Hao Chun Yang, Pei-Wei Lee, Wen-Hsiung Lu
  • Publication number: 20240118149
    Abstract: A stretchable strain sensor includes a light-emitting element, an optical structure, and a photo-detective element. The stretchable strain sensor is located in a path of light emitted from the light-emitting element. The optical structure is configured to have optical properties that change in response to stretching of at least a portion of the stretchable strain sensor. The photo-detective element is configured to detect light transmitted through the optical structure or reflected through the optical structure.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 11, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gae Hwang LEE, Youngjun YUN, Jong Won CHUNG, Yeongjun LEE, Won-Jae JOO, Yasutaka KUZUMOTO
  • Publication number: 20240120315
    Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Tze-Chiang Huang, Yun-Han Lee, Lee-Chung Lu
  • Publication number: 20240119836
    Abstract: Disclosed is a method for providing real-time bus information by a terminal, the method including: receiving ultra-precise bus information about buses scheduled to arrive at a bus stop from a server; and based on the ultra-precise bus information, displaying at least one bus which moves toward the bus stop and disappears after passing the bus stop on a map area.
    Type: Application
    Filed: June 22, 2023
    Publication date: April 11, 2024
    Inventors: Sukyung SON, Rakmin SUNG, Daehyun IM, Gyeonghyeon MOON, Yun Hee JUNG, Jaesung CHOI, Seoha YU, Binnara LEE, Jaiwuk CHUNG, Sung Hyeok PARK, Jinwoo KIM, Shin Hyun KIM, Gahee JEONG
  • Publication number: 20240120295
    Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.
    Type: Application
    Filed: January 30, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Hsien Lee, Yun-Chung Wu, Pei-Wei Lee, Fu Wei Liu, Jhao-Yi Wang
  • Patent number: 11951130
    Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: April 9, 2024
    Assignee: Eutilex Co., Ltd.
    Inventors: Byoung S. Kwon, Young Ho Kim, Kwang Hee Kim, Ji Won Chung, Young Gyoon Chang, Bo Rim Yi, Jung Yun Lee, Seung Hyun Lee, Sun Woo Im, Jin Kyung Choi, Hyun Tae Son, Eun Hye Yoo
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Publication number: 20240107999
    Abstract: Provided is an antibacterial composition comprising at least one compound including a quaternary ammonium structure having an acrylate group or a methacrylate group, and having an antibacterial strength A of 90% or more against at least one strain selected from Gram-positive bacteria and Gram-negative bacteria, and an acute oral toxicity dose LD50 of 300 mg/Kg or more, where the antibacterial strength A equals (1?Asample/AReference)×100, where Asample equals an absorbance of an inoculated medium solution incubated with the antibacterial composition, and AReference equals an absorbance of an inoculated medium solution incubated without addition of the antibacterial composition.
    Type: Application
    Filed: June 29, 2022
    Publication date: April 4, 2024
    Inventors: Ji Seok LEE, Soonhee KANG, Sanggon KIM, Leehyeon BAEK, Haesung YUN, Hwanhee LEE, Da Sol CHUNG, Seonjung JUNG, Hyungsam CHOI
  • Patent number: 11946051
    Abstract: The present invention relates to a pharmaceutical composition for preventing or treating hypertrophic scars. The present inventors have found that the inhibition of expression of TXNDC5, PRRC1, S100A11, Galectin 1, Filamin A, eIF-5A, Annexin A2, and FABP5 can be a new target for improving and treating hypertrophic scars. In the present invention, TXNDC5-, PRRC1-, S100A11-, Galectin 1-, Filamin A-, eIF-5A-, Annexin A2-, and FABP5-specific siRNAs were constructed to determine the probability of treating the hypertrophic scars. As a result, the knockdown of the protein or a gene encoding the protein induces apoptosis in the hypertrophic scars and reduces collagen expression, which can be very useful in treating wounds.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Tego Science Inc.
    Inventors: Saewha Jeon, Ho Yun Chung, Na Ra Oh, Yun Hee Kim, Jikhyon Han, Hyun Ah Moon
  • Publication number: 20240096757
    Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
  • Publication number: 20240081596
    Abstract: The present disclosure provides a surface cleaning apparatus that includes an illumination system having lighting to illuminate a floor surface or other area being cleaned. The lighting for the illumination system includes a plurality of lights, light sources, and/or lighting zones disposed around a housing of the apparatus. The illumination system can output a condition, status, state, alert or error to a user by emitting visible light and varying an intensity, color, wavelength, temperature, or animation of the light. Methods for operating the illumination system are also provided.
    Type: Application
    Filed: March 22, 2022
    Publication date: March 14, 2024
    Inventors: Sang Hoon Chung, Mike Luyckx, Chris J. Harmelink, Patryk Donald Akhurst, Isaac Busken-Jovanovich, Christopher L. Hogg, Churu Yun
  • Patent number: 11929206
    Abstract: A multilayer electronic component includes: a body including dielectric layers and having first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; side margin portions disposed on the fifth and sixth surfaces, respectively; and external electrodes disposed on the third and fourth surfaces, respectively. The body includes an active portion including internal electrodes disposed alternately with the dielectric layers in the first direction, one of the internal electrodes includes a central portion and an interface portion disposed between the central portion and one of the dielectric layers, and the interface portion and one of the side margin portions include Sn.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Jun Jung, Yun Kim, Hyun Kim, Sim Chung Kang, Eun Jung Lee
  • Publication number: 20240069028
    Abstract: Provided are biomarkers for predicting the prognosis of cervical cancer. In the case of using the biomarkers of the present disclosure, it is possible to select patients into a high-risk group, an intermediate-risk group, or a low-risk group, and thus, it is possible to provide tailored treatment for each patient according to prognosis prediction.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 29, 2024
    Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Hanbyoul Cho, Jae-Hoon Kim, Joon-Yong Chung, Hee Yun, Gwan Hee Han, Hye Rim Kim
  • Publication number: 20240071941
    Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Yun-Han Lee, Lee-Chung Lu
  • Patent number: 11904581
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer, and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution is 1:0.01-1. Moreover, the second polymer solution is composed of a second hydrophilic solution.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: February 20, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Yu-Chi Wang, Ming-Chia Yang, Yu-Bing Liou, Wei-Hong Chang, Yun-Han Lin, Hsin-Yi Hsu, Yun-Chung Teng, Chia-Jung Lu, Yi-Hsuan Lee, Jian-Wei Lin, Kun-Mao Kuo, Ching-Mei Chen