Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: In a management method and system for a shared radio unit and a computer-readable storage medium, N user groups are created for N operators, where N is a positive integer greater than 1; resources of the shared radio unit are divided into public resources and N private resources; the N user groups and the N private resources are bound correspondingly, and the N user groups are set to only have access to corresponding private resources bound in the N private resources; resource permissions of the shared radio unit are initialized, and account passwords configured for the N user groups are sent to the corresponding N operators respectively; and the N operators configures parameters to a data model language database according to the account passwords.

Abstract: A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.

Abstract: This application relates to compounds of Formula I: or pharmaceutically acceptable salts thereof, which are inhibitors of TAM kinases which are useful for the treatment of disorders such as cancer.

Abstract: A multifunctional single-interface electronic expansion device, comprising an external electronic expansion device and a power transmitting cable. The external electronic expansion device comprises a device body, an electrical connecting module, a data signal processing module, a power transmitting module, and a first assembling member. The device body comprises a first wall surface and a second wall surface. The electrical connecting module is disposed at the device body and is exposed from the first wall surface to be electrically connected with or detached from an interface of a first electronic device. The data signal processing module is electrically connected with the electrical connecting module. The power transmitting module is electrically connected with the electrical connecting module. The power transmitting module comprises a power transmitting interface exposed from the second wall surface.

Abstract: An active device, a semiconductor device and a semiconductor chip are provided. The active device includes: a channel layer; a top source/drain electrode, disposed at a top side of the channel layer; a first bottom source/drain electrode and a second bottom source/drain electrode, disposed at a bottom side of the channel layer; a first gate structure and a second gate structure, located between the top source/drain electrode and the first bottom source/drain electrode, wherein the first gate structure comprises a non-ferroelectric dielectric layer, and the second gate structure comprises a ferroelectric layer; and a third gate structure and a fourth gate structure, located between the top source/drain electrode and the second bottom source/drain electrode, wherein the third gate structure comprises a non-ferroelectric dielectric layer, and the fourth gate structure comprises a ferroelectric layer.

Abstract: A semiconductor device may include a non-volatile memory cell structure that may be formed in a back end region of a semiconductor device. The non-volatile memory cell structure may include a floating gate structure in which a portion of a dielectric layer is included between a gate structure and a word line conductive structure. The separation of the gate structure and the word line conductive structure by the dielectric layer results in the gate structure being a floating gate structure. This enables a charge to be selectively stored on the gate structure, even when power is removed from the word line conductive structure. The non-volatile memory cell structure along with a volatile memory cell structure are provided in the back end region of the semiconductor device, such that caching and long-term storage may be performed in the back end region of the semiconductor device.

Abstract: A capacitorless dynamic random access memory (DRAM) cell may include a plurality of transistors. At least a subset of the transistors may include a channel layer that approximately resembles an inverted U shape, an ohm symbol (?) shape, or an uppercase/capital omega (?) shape. The particular shape of the channel layer provides an increased channel length for the subset of the transistors, which may reduce the off current and may reduce current leakage in the subset of the transistors. The reduced off current and reduced current leakage may increase data retention in the subset of the transistors and/or may increase the reliability of the subset of the transistors without increasing the footprint of the subset of the transistors. Moreover, the particular shape of the channel layer enables the subset of the transistors to be formed with a top-gate structure, which provides low integration complexity with other transistors in the capacitorless DRAM cell.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A memory device, an operation method of a memory cell in a memory device and a semiconductor die are provided. A computational memory cell in the memory device includes: a field effect transistor (FET), with a changeable threshold voltage; and resistive storage devices, connected by a common terminal coupled to a source/drain terminal of the FET. By altering the threshold voltage of the FET, a logic function of the computational memory cell can be changed. During a logic operation, inputs are provided to the computational memory cell as resistance states of the resistive storage devices, and a current passing through a conduction channel of the FET is functioned as an output for the logic operation.

Abstract: A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.

Abstract: A memory integrated circuit is provided. The memory integrated circuit includes a first memory array, a second memory array and a driving circuit. The first and second memory arrays are laterally spaced apart, and respectively include: memory cells, each including an access transistor and a storage capacitor coupled to the access transistor; bit lines, respectively coupled to a row of the memory cells; and word lines, respectively coupled to a column of the memory cells. The driving circuit is disposed below the first and second memory arrays, and includes sense amplifiers. Each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

Abstract: A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.

Abstract: The present disclosure provides a fire source detection method and device under the condition of a small sample size, and a storage medium, and belongs to the field of target detection and industrial deployment. The method includes the steps of acquiring fire source image data from an industrial site; constructing a fire source detection model; inputting the fire source image data to the fire source detection model, and analyzing the fire source image data via the fire source detection model to obtain a detection result, where the detection result includes a specific location, precision and type of a fire source. By means of the method, the problems of insufficient sample capacity and difficulty in training under the condition of a small sample size are solved, and different enhancement methods are used to greatly increase the number and quality of samples and improve the over-fitting ability of models.

Abstract: The present invention provides ocular cells, genetically modified by a CRISPR system targeting the expression of B2M for ocular cell therapy. The invention further provides methods of generating an expanded population of genetically modified ocular cells, for example limbal stem cells (LSCs) or corneal endothelial cells (CECs), wherein the cells are expanded involving the use of a LATS inhibitor and the expression of B2M in the cells has been reduced or eliminated. The present invention also provides cell populations, preparations, uses and methods of therapy comprising said cells.

Abstract: A cable-winding charger includes a housing, a main circuit board, a plug, a pivot base, a torsion spring, and a data cable. The main circuit board is in the housing and includes conductive rings. The conductive rings are coaxially arranged around the column of the housing. The plug is pivotally connected to the housing and electrically connected to the main circuit board. The pivot base is pivotally connected to the housing. Each conductive piece of the pivot base contacts the corresponding conductive ring. One end of the torsion spring is fixed to the column, and the other end of the torsion spring is fixed to the pivot base. One end of the cable body of the data cable is electrically connected to the conductive pieces, and the other end of the cable body is electrically connected to the connection port.