Abstract: According to one embodiment of the present invention, a method for reconstructing client web page accesses is provided that comprises capturing network-level information for client accesses of at least one web page. The method further comprises constructing a knowledge base of reliable information identifying content of at least one web page, and reconstructing at least one client web page access from the captured network-level information using the reliable information of the knowledge base.

Abstract: A vise has a first clamp seat, a second clamp seat engaging with the first clamp seat, a first clamp plate fastened on the first clamp seat, a second clamp plate fastened on the second clamp seat, a taper block disposed between the first clamp seat and the second clamp seat, a taper collar disposed on the taper block, a pair of coiled springs, a pair of fastening bolts, an adjustment bolt, and a nut. The first clamp seat has an inclined face, a notch, a recessed face, and a pair of through holes. The second clamp seat has an inclined face, a notch, a recessed face, and a pair of threaded apertures. The taper block has an oblong hole. The coiled springs are inserted in the through holes of the first clamp seat. The fastening bolts pass through the coiled springs to fasten the first clamp seat and the second clamp seat together. The adjustment bolt pass through the taper collar and the taper block. The nut engages with the adjustment bolt.

Abstract: Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said silicon nitride layer. Suitable materials for the buffer layer that have been found to be effective include silicon oxide and silicon oxynitride with the latter offering some additional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

Abstract: A process for forming a contact hole opening, featuring the use in situ dry etching, and photoresist removal procedures, used to define the desired contact hole opening; in an overlying hard mask layer, in the dielectric layer, and in an underlying insulator stop layer, has been developed. The process features the initial definition of the contact hole opening, in an overlying hard mask insulator layer, accomplished in a chamber of a dry etch tool, followed by removal of an overlying, contact hole defining photoresist shape, performed in situ, in the same dry etch chamber. The contact hole opening is then transferred to the dielectric layer via a selective dry etch procedure, performed in situ, in the dry etch chamber, using the overlying hard mask insulator layer as an etch mask.

Abstract: Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said silicon nitride layer. Suitable materials for the buffer layer that have been found to be effective include silicon oxide and silicon oxynitride with the latter offering some additional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

Abstract: A process for forming a composite, interlevel dielectric, (ILD), layer, for MOSFET devices, has been developed. The composite ILD layer is comprised with an underlying, undoped silicon glass layer, providing the material needed to fill the narrow spaces between polysilicon gate structures of the MOSFET devices. A P2O5 doped, insulator layer, is next formed on the underlying, undoped silicon glass layer, to provide a mobile ion gettering property. An overlying, undoped silicon glass layer is then deposited and subjected to a chemical mechanical polishing procedure, resulting in the desired planar top surface topography, for the composite ILD layer.

Abstract: A method of forming a composite dielectric layer comprising the following steps. A structure having at least two semiconductor structures separated by a gap therebetween is provided. A first dielectric layer is formed over the structure, the two semiconductor structures and within the gap between the two semiconductor structures to a thickness as least as high as the top of the semiconductor structures by a first high density plasma (HDP) process. The first HDP process having a first high bias RF power, a low first deposition: sputter ratio and a first chucking bias voltage. A second dielectric layer is then formed over the first dielectric layer by a second HDP process to form the composite dielectric layer. The second HDP process having: a second bias RF power that is less than the first bias RF power; a second deposition: sputter ratio that is greater than the first deposition: sputter ratio; and a second chucking bias voltage that is zero.

Abstract: Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted. Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said sidon nitride layer. Suitable materials for the buffer layer that have been found to be infective include silicon oxide and silicon oxynitride with the latter offering some ditional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

Abstract: A method for shallow trench isolation formation having a thick un-biased HDP USG liner layer to reduce HDP-CVD induced defects is described. Trenches are etched through an etch stop layer into a semiconductor substrate. The semiconductor substrate is thermally oxidized to form a thermal liner layer within the isolation trenches. The isolation trenches are filled using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein the HDP-CVD process comprises: first depositing a first liner layer overlying the thermal liner layer wherein no bias power is supplied during the first depositing step and wherein the first liner layer has a thickness of between 200 and 400 Angstroms, second depositing a second liner layer using low bias power, and third depositing a gap filling layer overlying the second liner layer to fill the isolation trenches. The gap filling layer is polished back overlying the etch stop layer.

Abstract: A method for significantly reducing plasma damage during the deposition of inter-layer dielectric (ILD) gapfills on topographic substrates by high density plasma chemical vapor deposition (HDP-CVD). The method can also be applied to the deposition of dielectric layers on silicon oxide covered substrates. The method provides a modification of current state of the art practices in HDP-CVD by a novel variation in the RF input power to the plasma processing chamber during certain portions of the processing cycle. Specifically, top/side RF power is reduced from 3000W/4000W to 1300W/3100W during the heat-up portion of the cycle and plasma lift is eliminated during the wafer release and lift portion of the cycle by turning off the 1000W/2000W top/side RF power. A method for determining the degree of plasma induced damage by measurement of a flatband voltage is also provided.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a dieletric layer with improved physical properties. There is first provided a substrate. There is then formed over the substrate a series of lines which constitute a patterned microelectronics layer. There is then formed over the patterned microelectronics layer and substrate a conformal dielectric layer. There is then formed over the substrate a second dielectric layer. There is then formed over the substrate a third dielectric layer formed of silicon oxide dielectric material employing high density plasma chemical vapor deposition (HDP-CVD) to complete a composite inter-level metal dielectric (IMD) layer. A fourth dielectric layer formed employing silicon containing dielectric material may be formed over the substrate and third dielectric layer to complete an inter-level metal dielectric (IMD) layer.

Abstract: A method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths and the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket first aperture fill layer. The blanket first aperture fill layer is formed employing a first simultaneous deposition and sputter method.

Abstract: The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicone gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer.

Abstract: The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si- Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC).

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a dielectric passivating layer with attenuated delamination and improved adhesion to subsequent passivating and encapsulating materials. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a patterned microelectronics layer. There is then formed over the substrate a silicon containing dielectric layer employing high density plasma chemical vapor deposition (IDP-CVD) in two steps, wherein the conditions of the HDP-CVD process are optimized during the second step to provide a final layer portion with a greater degree of surface topography. Subsequently there are formed over the substrate an additional passivation layer with attenuated delamination and an organic polymer overcoat layer with improved adhesion.

Abstract: Within a method for forming an aperture fill layer within an aperture there is first provided a topographic substrate which has formed therein a pair of mesas which defines an aperture. There is then formed over the topographic substrate and into the aperture a blanket aperture fill layer while employing a high density plasma chemical vapor deposition (HDP-CVD) method, where the blanket aperture fill layer is formed to a thickness greater than a depth of the aperture while forming a pair of protrusions over the pair of mesas. There is then etched, while employing a sputter etch method, the blanket aperture fill layer to form an etched blanket aperture fill layer such that the pair of protrusions of the blanket aperture fill layer formed over the pair of mesas is etched more rapidly than a portion of the blanket aperture fill layer formed within the aperture.

Abstract: A connection terminal for use with a flat flexible connector comprises a base defining first and second sides. A pair of cantilevered arms extends forward from the base. Each arm forms a contact portion at a free end thereof. Characterized in that the contact portion has reduced thickness than the rest of the terminal.

Abstract: The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer.

Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for forming and then later removing a silicon oxynitride, SiON, anti-reflection coating (ARC) over a semiconductor substrate, for the purpose of enhancing the resolution of photolithographically defined sub-micron polysilicon gates. The problem addressed by this invention is that the SiON ARC must first be used to reduce optical reflection from a blanket polysilicon surface, during the photolithography exposure step that defines the sub-micron polysilicon gate features, and then the ARC must be removed by a wet etch process that will not chemically attack the gate oxide under the polysilicon gate features or any exposed polysilicon surfaces.

Abstract: A new method of forming a non-shrinkable metal passivation layer that will eliminate metal voiding and improve electromigration lifetime of the integrated circuit device is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered by an insulating layer. A metal layer is deposited overlying the insulating layer and patterned to form metal lines wherein there is a gap between two of the metal lines. A non-shrinkable passivation layer is formed according to the following steps: 1) a HDP-CVD oxide layer is deposited overlying the metal lines wherein the gap is filled by the HDP-CVD oxide layer. 2) A silicon nitride layer is deposited by plasma-enhanced chemical vapor deposition overlying the HDP-CVD oxide layer. Or, 1) a PECVD oxide layer is deposited over the metal lines. 2) A silicon nitride layer is deposited by PECVD over the oxide layer to fill the gap and complete the passivation. Then, the fabrication of the integrated circuit device is completed.