Patents by Inventor Yun-Han Chen
Yun-Han Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128194Abstract: Integrated circuit packages and methods of forming the same are provided. In an embodiment, a device includes: a power distribution interposer including: a first bonding layer; a first die connector in the first bonding layer; and a back-side interconnect structure including a power rail connected to the first die connector; and an integrated circuit die including: a second bonding layer directly bonded to the first bonding layer by dielectric-to-dielectric bonds; a second die connector in the second bonding layer, the second die connector directly bonded to the first die connector by metal-to-metal bonds; and a device layer on the second bonding layer, the device layer including a contact and a transistor, the transistor including a first source/drain region, the contact connecting a back-side of the first source/drain region to the second die connector.Type: ApplicationFiled: January 9, 2023Publication date: April 18, 2024Inventors: Ming-Fa Chen, Yun-Han Lee, Lee-Chung Lu
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Publication number: 20240120315Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.Type: ApplicationFiled: February 15, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, Tze-Chiang Huang, Yun-Han Lee, Lee-Chung Lu
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Patent number: 11955245Abstract: A method and a system for mental index prediction are provided. The method includes the following steps. A plurality of images of a subject person are obtained. A plurality of emotion tags of the subject person in the images are analyzed. A plurality of integrated emotion tags in a plurality of predetermined time periods are calculated according to the emotion tags respectively corresponding to the images. A plurality of preferred features are determined according to the integrated emotion tags. A mental index prediction model is established according to the preferred features to predict a mental index according to the emotional index prediction model.Type: GrantFiled: July 2, 2021Date of Patent: April 9, 2024Assignees: Acer Incorporated, National Yang Ming Chiao Tung UniversityInventors: Chun-Hsien Li, Szu-Chieh Wang, Andy Ho, Liang-Kung Chen, Jun-Hong Chen, Li-Ning Peng, Tsung-Han Yang, Yun-Hsuan Chan, Tsung-Hsien Tsai
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Publication number: 20240071941Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, Yun-Han Lee, Lee-Chung Lu
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Patent number: 11916155Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
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Patent number: 11687135Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: September 20, 2021Date of Patent: June 27, 2023Assignee: Tahoe Research, Ltd.Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 11362464Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.Type: GrantFiled: September 22, 2020Date of Patent: June 14, 2022Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Patent number: 11316305Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.Type: GrantFiled: September 22, 2020Date of Patent: April 26, 2022Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Publication number: 20220052488Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.Type: ApplicationFiled: September 22, 2020Publication date: February 17, 2022Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Publication number: 20220052489Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.Type: ApplicationFiled: September 22, 2020Publication date: February 17, 2022Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Publication number: 20220004237Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 11157052Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: September 23, 2019Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 11114770Abstract: An antenna structure suitable for 5G use includes first and second antenna units. Each second antenna unit is positioned between adjacent first antenna units. Each first antenna unit is positioned between adjacent second antenna units. Each first antenna unit and each second antenna unit are restricted to emit a radio beam in a single polarization. The first antenna unit emits radio waves in a first polarization, the second antenna unit emits waves in a second polarization. The first polarization direction and the second polarization direction are perpendicular to each other.Type: GrantFiled: November 14, 2019Date of Patent: September 7, 2021Assignee: Shenzhen Next Generation Communications LimitedInventors: Kuo-Cheng Chen, Jian-Wei Chang, Zheng Lin, Jia Chen, Ke-Jia Lin, Yun-Han Chen
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Publication number: 20200176891Abstract: An antenna structure suitable for 5G use includes first and second antenna units. Each second antenna unit is positioned between adjacent first antenna units. Each first antenna unit is positioned between adjacent second antenna units. Each first antenna unit and each second antenna unit are restricted to emit a radio beam in a single polarization. The first antenna unit emits radio waves in a first polarization, the second antenna unit emits waves in a second polarization. The first polarization direction and the second polarization direction are perpendicular to each other.Type: ApplicationFiled: November 14, 2019Publication date: June 4, 2020Applicant: Shenzhen Next Generation Communications LimitedInventors: KUO-CHENG CHEN, JIAN-WEI CHANG, ZHENG LIN, JIA CHEN, KE-JIA LIN, YUN-HAN CHEN
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Patent number: 10568200Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Patent number: 10568199Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Patent number: 10568198Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 1, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Publication number: 20200019221Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: September 23, 2019Publication date: January 16, 2020Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 10429913Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: August 7, 2018Date of Patent: October 1, 2019Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 10409346Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: August 7, 2018Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam