Abstract: A three-dimensional flash memory including an intermediate wiring layer and a method of manufacturing the same are disclosed.

Abstract: The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Abstract: A three-dimensional flash memory including floating devices and a manufacturing method therefor are disclosed.

Abstract: Disclosed are a three-dimensional flash memory for improving contact resistance of IGZO channel layer and a method for manufacturing same. According to one embodiment, the three-dimensional flash memory may comprise: multiple word lines sequentially stacked and extending in a horizontal direction on a substrate; and at least one string extending in a vertical direction on the substrate through the multiple word lines, the at least one string comprising a channel layer extending in the vertical direction and a charge storage layer formed to surround the channel layer, wherein the at least one string comprises a drain junction formed in a dual structure and comprising an N+ doped first area on the channel layer and an N+ doped second area with a material having lower contact resistance than the channel layer.

Abstract: Disclosed are: a three-dimensional flash memory including a channel layer having a multilayer structure; and a method for manufacturing same. The channel layer has a dual structure including a first channel layer which is formed to be in contact with a charge storage layer and improves the electron mobility in an inversion region that is a contact interface with the charge storage layer, and a second channel layer formed on an inner wall of the first channel layer. Alternatively, the channel layer can have a dual structure including an outer first channel layer and a second channel layer formed on an inner wall of the first channel layer, wherein a heterojunction is formed as a junction between the first channel layer and the second channel layer.

Abstract: A three dimensional semiconductor device is disclosed. The tree dimensional semiconductor device includes a word line stack over a substrate and a channel pillar structure passing through the word line stack in a vertical direction perpendicular to a top surface of the substrate. The channel pillar structure includes a channel structure. The channel structure includes a blocking layer, a trap layer, a tunneling layer, a channel layer, a filling layer, and a back gate electrode. The channel structure has a pillar shape.

Abstract: Provided are a three-dimensional semiconductor memory device, a method for manufacturing the same, a method for operating the same, and an electronic system including the same. The three-dimensional semiconductor memory device includes a substrate, a stack structure on the substrate, and vertical channel structures, which are provided in channel holes penetrating the stack structure, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, a conductive pad, and a vertical semiconductor pattern, wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern, and wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween.

Abstract: Disclosed are a three-dimensional flash memory, to which a GSL-removed structure is applied, and an operating method thereof.

Abstract: According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

Abstract: A three-dimensional flash memory for promoting integration, and a manufacturing method therefor are disclosed. The three-dimensional flash memory to which a cell on peripheral circuit (COP) structure is applied comprises: a substrate having at least one transistor of a peripheral circuit, formed according to the COP structure; at least one memory cell string formed to extend in one direction above the at least one transistor; and a common source line commonly used by means of the at least one transistor and the at least one memory cell string.

Abstract: Disclosed is a three-dimensional flash memory using a ferroelectric layer on the basis of a back gate structure.

Abstract: A three-dimensional flash memory for improving leakage current and a substrate are disclosed. The three-dimensional flash memory comprises: a string extending in one direction on the substrate, wherein the string includes a channel layer extending in the one direction and a charge storage layer extending in the one direction so as to surround the channel layer; at least one selection line vertically connected to an upper end or a lower end of the string; and a plurality of word lines positioned above or below the at least one selection line and vertically connected to the string, wherein the channel layer is formed of an oxide semiconductor material.

Abstract: The present invention relates to a three-dimension flash memory to which an efficient word line connection structure is applied, and a method for manufacturing same, wherein a plurality of word lines are connected to a low decoder respectively through contacts of the plurality of word lines, a plurality of connection wires, and plug vias of the plurality of word lines. The row decoder and a column decoder are arranged to divide a plurality of peripheral circuit blocks such that the plurality of peripheral circuit blocks are symmetrical to each other in the plane of the three-dimensional flash memory. The three-dimension flash memory is configured in a buried type in which a common source line is buried in a substrate, in order to improve integration density.

Abstract: A through silicon via (TSV)-based three-dimensional flash memory having a high degree of integration comprises: at least one memory cell string chip including a plurality of memory cell strings; and a peripheral circuit chip including at least one peripheral circuit, wherein the peripheral circuit chip is arranged below the at least one memory cell string chip and is connected to the at least one memory cell string chip by using at least one TSV. The at least one memory cell string chip includes the plurality of memory cell strings, and the peripheral circuit chip is connected to the at least one peripheral circuit. The peripheral circuit chip is connected to the at least one memory cell string chip by using the at least one TSV extending through the at least one memory cell string chip.

Abstract: Disclosed is a three-dimensional flash memory including a back gate, which includes word lines extended and formed in a horizontal direction on a substrate so as to be sequentially stacked, and strings penetrating the word lines and extended and formed in one direction on the substrate. Each of the strings includes a channel layer extended and formed in the one direction, and a charge storage layer extended and formed in the one direction to surround the channel layer, the channel layer and the charge storage layer constitute memory cells corresponding to the word lines, and the channel layer includes a back gate extended and formed in the one direction, with at least a portion of the back gate surrounded by the channel layer, and an insulating layer extended and formed in one direction between the back gate and the channel layer.

Abstract: Disclosed is a three 3D flash memory having an improved structure and a method for manufacturing the same.

Abstract: A three-dimensional flash memory is provided, and technique to suppress interference caused by an inter-cell insulation layer in a vertical cell and to form a stable vertical channel layer, a technique to reduce a length of wire than a conventional three-dimensional flash memory for overcoming problems of deterioration of chip characteristics such as operation speed and power consumption and difficulty of wiring technique in the manufacturing process, and a technique to improve horizontal density of channel layers and ONO layers are proposed.

Abstract: Disclosed is a method of manufacturing a three-dimensional semiconductor memory device including a ferroelectric thin film. The method includes forming a mold structure including interlayer dielectric layers and sacrificial layers alternately stacked on a substrate, forming channel holes penetrating the mold structure, forming vertical channel structures inside the channel holes, forming an isolation trench penetrating the mold structure and having a line shape extending in one direction, selectively removing the sacrificial layers exposed by the isolation trench, forming gate electrodes filling a space from which the sacrificial layers are removed, and performing a heat treatment process and a cooling process for the vertical channel structures.

Abstract: Disclosed are a three-dimensional flash memory, which reduces leakage current and supports a hole injection erase technique, and a method for manufacturing same. According to an embodiment, the three-dimensional flash memory comprises: a substrate; a channel layer extending in one direction on the substrate and having the shape of a hollow macaroni; and a P-type filer extending in the one direction while filling the inner space of the channel layer.

Abstract: A three-dimensional flash memory is provided, and technique to suppress interference caused by an inter-cell insulation layer in a vertical cell and to form a stable vertical channel layer, a technique to reduce a length of wire than a conventional three-dimensional flash memory for overcoming problems of deterioration of chip characteristics such as operation speed and power consumption and difficulty of wiring technique in the manufacturing process, and a technique to improve horizontal density of channel layers and ONO layers are proposed.