Abstract: Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.

Abstract: Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.

Abstract: Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: Devices that have bonding pads, and methods for fabricating the same. The bonding pads have two conductive layers, and an intermediate layer between them. The intermediate layer has a hybrid configuration of a relatively large conductive plate section, and a mixed plugs/mesh section. The plugs/mesh section has conductive portions interspersed with non-conducting portions, with features that are relatively small in size. The hybrid configuration achieves a proper balance between the plate section for the main electrical contact, and the plugs/mesh section for support and additional current density.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: Disclosed is a method for fabricating a NOR flash memory device where a buried common source line made of an impurity diffusion layer has an even surface or a lower step difference. The method includes forming adjacent isolation layers that define an active region there between within a semiconductor substrate. Then, a floating gate pattern is formed overlying the active region. An inter-gate dielectric film and a control gate film are sequentially formed overlying the floating gate pattern. The control gate film, the inter-gate dielectric film, and the floating gate pattern are sequentially patterned, thereby forming a plurality of word lines extending across the active region. The active region between the adjacent isolation layers and the isolation layers are removed, adjacent to one sidewall of the word lines, thereby forming a common source line region. Next, impurities are implanted into the common source line region, thereby forming a common source line made of an impurity diffusion layer.

Abstract: Devices that have bonding pads, and methods for fabricating the same. The bonding pads have two conductive layers, and an intermediate layer between them. The intermediate layer has a hybrid configuration of a relatively large conductive plate section, and a mixed plugs/mesh section. The plugs/mesh section has conductive portions interspersed with non-conducting portions, with features that are relatively small in size. The hybrid configuration achieves a proper balance between the plate section for the main electrical contact, and the plugs/mesh section for support and additional current density.

Abstract: A method for managing memory cells in a nonvolatile memory, such as a flash memory, includes detecting and intermediately programming fast-erased memory cells. All of the memory cells in a sector can then be erased.

Abstract: Disclosed is a method for fabricating a NOR flash memory device where a buried common source line made of an impurity diffusion layer has an even surface or a lower step difference. The method includes forming adjacent isolation layers that define an active region there between within a semiconductor substrate. Then, a floating gate pattern is formed overlying the active region. An inter-gate dielectric film and a control gate film are sequentially formed overlying the floating gate pattern. The control gate film, the inter-gate dielectric film, and the floating gate pattern are sequentially patterned, thereby forming a plurality of word lines extending across the active region. The active region between the adjacent isolation layers and the isolation layers are removed, adjacent to one sidewall of the word lines, thereby forming a common source line region. Next, impurities are implanted into the common source line region, thereby forming a common source line made of an impurity diffusion layer.

Abstract: A method for managing memory cells in a nonvolatile memory, such as a flash memory, includes detecting and intermediately programming fast-erased memory cells. All of the memory cells in a sector can then be erased.