Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Abstract: A method for controlling carbide network in a bearing steel wire rod by controlling cooling and rolling, comprises the following steps: rapidly rolling a bar to a wire rod and spinning it into a loose coil, controlling the rolling temperature at 780° C.-880° C.; and the spinning temperature at 750° C.-850° C.; carrying out on-line controlling cooling of continuous loose coils using EDC water bath austempering cooling process, controlling the cooling rate at 2.0° C./s-10° C./s, and controlling the final cooling temperature within 620-630° C.; after EDC water bath austempering cooling, using slow cooling under a cover, and the temperature is controlled to be 400° C.-500° C. when being removed out of the cover; after slow cooling, collecting coils, and cooling in air to the room temperature.

Abstract: A moisture-permeable composite membrane is manufactured by the step of subjecting a mixture to a crosslinking treatment. The mixture contains a polyisoprene, a polyurethane with a polar functional group, a crosslinking agent, and a vulcanizing agent. In the mixture, a weight ratio of the polyurethane with the polar functional group to the polyisoprene ranges from 1:0.55 to 1:6.60. A method for manufacturing the moisture-permeable composite membrane is also provided.

Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

Abstract: Implementations of the subject matter described herein relate to generating animated infographics from static infographics. A computer-implemented method comprises: extracting visual elements of a static infographic; determining, based on the visual elements, a structure of the static infographic at least indicating a layout of the visual elements in the static infographic; and applying a dynamic effect to the visual elements based on the structure of the static infographic to generate an animated infographic.

Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

Abstract: A wafer map recognition method using artificial intelligence includes obtaining wafer maps of a plurality of wafers; performing an unsupervised algorithm on the wafer map of each wafer in the plurality of wafers to generate a feature data set for the corresponding wafer map; and performing a clustering algorithm according to a plurality of feature data sets for the plurality of wafer maps to find a wafer map with a potential defect.

Abstract: A device includes a first die, an interconnect structure, a RDL layer, a guard structure and an underfill layer. The interconnect structure is electrically connected to the first die. The RDL layer is disposed in a dielectric layer. The guard structure is disposed in the dielectric layer to define a connector region, wherein the guard structure and the interconnect structure are disposed on opposite sides of the die. The underfill layer surrounds the interconnect structure, the first die and the guard structure, wherein the underfill layer is kept outside of the connector region by the guard structure.

Abstract: The embodiments of the disclosure provide a tracking accuracy evaluating system, a tracking accuracy evaluating device, and a tracking accuracy evaluating method. The method includes: detecting multiple distances between the tracking accuracy evaluating device and multiple reference positions in a rotating process associated with a rotating axis, wherein an accommodating space of the tracking accuracy evaluating device accommodates a tracking device during the rotating process, and the distance sensor, the rotating axis, and the tracking device accommodated in the accommodating space have a fixed relative position therebetween; estimating a first pose variation of the tracking device during the rotating process based on the distances and the fixed relative position; obtaining a second pose variation of the tracking device during the rotating process; and determining a tracking accuracy of the tracking device based on the first pose variation and the second pose variation.

Abstract: A silicon-carbon composite negative electrode material containing a lithium-rich long-chain composite salt, comprises a silicon-carbon composite material slurry and a lithium-rich long-chain composite salt. Each silicon-carbon composite material particle comprises an element-doped silicon-containing nanoparticle, a first carbon-based covering layer and a second carbon-based covering layer. The element-doped silicon-containing nanoparticle is a core, the first carbon-based covering layer is coated on a surface of the element-doped silicon-containing nanoparticle, the second carbon-based covering layer is coated on the first carbon-based covering layer. The lithium-rich long-chain composite salt comprises a plurality of composite ion bridging structures. A method for preparing the silicon-carbon composite negative electrode material containing a lithium-rich long-chain composite salt is further provided.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. Three elliptic curve cryptographic instructions are proposed in the instruction set architecture for key exchange between an initiator and a responder. The initiator device executes the first elliptic curve cryptographic instruction to generate a key pair (rA, RA). In addition to considering the first temporary public key RA, the responder device further takes the second temporary public key RB into consideration when executing the second elliptic curve cryptographic instruction to generate the responder-generated shared key KB. Based on the temporary private key rA, and the temporary public keys RA and RB, the initiator device executes the third elliptic curve cryptographic instruction to generate the initiator-generated shared key KA.

Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Abstract: A synchronized rectification control method for use in a flyback converter is provided. The flyback converter includes a transformer including a secondary winding, a synchronous rectifier switch and a synchronous rectifier controller. The synchronous rectifier switch is coupled to the secondary winding and the synchronous rectifier controller, and is used to output a voltage difference signal and receive a control voltage. The method includes the synchronous rectifier controller detecting a rapid falling edge of the voltage difference signal to generate a rapid falling edge signal, generating an envelope signal according to the voltage difference signal, generating a time length control signal according to the voltage difference signal and the envelope signal, generating a blanking time signal according to the voltage difference signal and the time length control signal, and performing a logic operation on the blanking time signal and the rapid falling edge signal to generate the control voltage.

Abstract: A controller and a control method for an asymmetric half-bridge power supply are disclosed. The asymmetric half-bridge power supply includes a first arm switch and a second arm switch forming a half-bridge, and a resonant circuit connected to the half-bridge. The method includes providing a duration parameter reflecting a second turn-on time of the second arm switch in a earlier switching cycle; providing a control signal to turn on the first arm switch for a first turn-on time in a later switching cycle; detecting whether the first arm switch has performed ZVS in response to a signal edge of the control signal to adjust the duration parameter accordingly; determining the second turn-on time of the second arm switch in the later switching cycle based on the duration parameter; and turning on the second arm switch for the second turn-on time after the first turn-on time in the later switching cycle.

Abstract: A device and a method for detecting a light irradiating angle are disclosed. The device, used to detect the incident direction of a light ray, includes a solar sensor and a processor. The sensing unit of the solar sensor has sensing areas. The sensing areas correspondingly generate sensing signals based on the intensity of the light ray. A mask covers the sensing unit and has an X-shaped light transmitting portion. The light ray transmits the X-shaped light transmitting portion to form an X-axis light ray and a Y-axis light ray. The X-axis light ray intersects the Y-axis light ray. The X-axis light ray and the Y-axis light ray fall on the sensing area. The processor, coupled to the sensing unit, receives the sensing signals and determines information of the incident direction according to the sensing signals.

Abstract: A drug conjugate includes a structure shown by the following formula: Z-(linker-[R]m)n. In the formula, Z is a drug compound, R is a sugar, and m and n are independently an integer from 1 to 6. The drug compound Z is a hepatitis virus targeting drug, a hepatitis B virus (HBV) drug, an inhibitor of apoptosis protein (IAP) antagonist, a multidrug resistance (MDR) inhibitor, or analogues, precursors, prodrugs, derivatives thereof.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: A display panel and a driving baseplate, relate to the technical field of displaying. The display panel includes an active area and a peripheral area located on at least one side of the active area, and the display panel includes: a driving baseplate, including a substrate and a conducting ring embedded on a surface of one side of the substrate, wherein the conducting ring is located in the peripheral area; a light emitting device, located in the active area and disposed on a side of the driving baseplate close to the conducting ring; an isolation dam, located in the peripheral area and disposed on a side of the conducting ring away from the substrate, wherein the isolation dam overlaps with the conducting ring; and an encapsulation layer, disposed on sides of the light emitting device and the isolation dam away from the substrate.

Abstract: An optical lens assembly includes a stop, and includes, in order from an object side to an image side: a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens, wherein an incident angle where a main light is incident on an image plane at a maximum view angle of the optical lens assembly is CRA, a maximum optical effective radius of the image-side surface of the sixth lens is CA62, and the following conditions are satisfied: 9.27<CRA/CA62<20.02.

Abstract: An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.