Patents by Inventor Yun Huang

Yun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250112088
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chin LEE, Yen Ju WU, Shao-Kuan LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Jing Ting SU, Kai-Fang CHENG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
  • Publication number: 20250107722
    Abstract: A sensing module includes a first coil, a control component coupled to the first coil, and a shielding component positioned at least on a first side of the first coil. The control component is configured to drive the first coil to transmit a first emitting electromagnetic signal, and to receive an induction signal generated from the first coil induced due to a first feedback electromagnetic signal. The shielding component shields at least a portion of the first emitting electromagnetic signal transmitting toward a first direction.
    Type: Application
    Filed: March 5, 2024
    Publication date: April 3, 2025
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: TING-WEI WANG, CHIU-YUN HUANG
  • Publication number: 20250111322
    Abstract: A carbon emission calculation system and a carbon emission calculation method are provided. The carbon emission calculation system includes a computing equipment and a detection element. The detection element is coupled to the computing equipment and disposed in a mobile vehicle. When the detection element detects a user identity, the detection element outputs inbound data to the computing equipment, and the computing equipment starts to calculate usage information according to the inbound data. When the detection element detects the user identity again, the detection element outputs outbound data to the computing equipment, and the computing equipment finishes calculating the usage information according to the outbound data. The computing equipment calculates a personal carbon emission according to the inbound data, the outbound data, and the usage information.
    Type: Application
    Filed: April 24, 2024
    Publication date: April 3, 2025
    Applicant: APh ePower Co., Ltd.
    Inventors: Yi-Yun Huang, Hsiu-Hsien Su
  • Publication number: 20250111650
    Abstract: A deep learning method of an artificial intelligence model for medical image recognition is provided. The method includes the following steps: obtaining a first image set, where the first image set includes at least two images captured with different parameters; performing image pre-processing on each image of the first image set to obtain a second image set; performing image augmentation on the second image set to obtain a third image set; adding the third image set to a training image data set; and training the artificial intelligence model using the training image data set.
    Type: Application
    Filed: February 15, 2024
    Publication date: April 3, 2025
    Inventors: Chia-Yuan CHANG, Chen-Hwa SUNG, Gigin LIN, Tzu-Hsiang YANG, Tzu-Yun WANG, Chien-Yu HUANG
  • Patent number: 12266703
    Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Che Lin, Po-Yu Huang, I-Wen Wu, Chen-Ming Lee, Chia-Hsien Yao, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12264102
    Abstract: A method for producing photocatalytic mortar includes providing a mortar-producing material including a fine aggregate and cement, a reactant mixture including a zinc source and urea, and a microorganism-containing mixture including water and a urease-producing microorganism, subjecting the microorganism-containing mixture and the reactant mixture to microbial induced precipitation in the mortar-producing material, subjecting zinc carbonate crystal-containing mortar produced to curing for the same to undergo hydration, and subjecting cured mortar to hydrothermal synthesis, so that zinc carbonate crystals therein are converted to nano zinc oxide crystals.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 1, 2025
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Chien-Yen Chen, Yi-Hsun Huang, Pin-Yun Lin, Wei-Fan Ye
  • Patent number: 12267048
    Abstract: A common-emitter amplifier with unilateral pre-embedding inductors includes: an input matching circuit, a first-stage amplification circuit, a first-stage interstage matching circuit, a second-stage amplification circuit, a second-stage interstage matching circuit, a third-stage amplification circuit, and an output matching circuit. The common-emitter amplifier is configured to: make an input signal sequentially enter bases of common-emitter transistors of the first-stage, second-stage, and third-stage amplification circuits, make the input signal be amplified stage by stage by the common-emitter transistors, and finally make an amplified input signal obtained by amplifying of each common-emitter transistor output through a collector of each common-emitter transistor. The common-emitter amplifier is configured to introduce interstage staggered tuning to expand bandwidth to address a narrowband problem.
    Type: Grant
    Filed: December 9, 2024
    Date of Patent: April 1, 2025
    Assignee: Beijing University of Posts and Telecommunications
    Inventors: Jianguo Yu, Xiaorui Liu, Yun Wang, Kaile Li, Yibo Huang, Feixiang Zhang, Zhihe Wu
  • Patent number: 12266606
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yu Huang, Chia-Hsien Yao, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250105169
    Abstract: A semiconductor package includes a semiconductor die, an interposer disposed below the semiconductor die, first joints electrically coupling the semiconductor die to the interposer, at least one second joint coupling the semiconductor die to the interposer, and a first underfill disposed between the semiconductor die and the interposer to surround the active and second joints. The semiconductor die includes a first region, a seal ring region surrounding the first region, and a second region between the seal ring region and a die edge. The first joints are located within the first region, and the second joint is disposed at a die corner within the second region and is electrically floating in the semiconductor package.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Leu-Jen Chen, Wen-Wei Shen, Kuan-Yu Huang, Yu-Shun Lin, Sung-Hui Huang, Hsien-Pin Hu, Shang-Yun Hou
  • Patent number: 12253729
    Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Publication number: 20250086134
    Abstract: In one embodiment, a method for controlling PCIe devices on an autonomous driving system (ADS) of an autonomous driving vehicle (ADV) is disclosed. The method includes scanning PCIe ports of the ADS to discover PCIe device(s) mounted on the ADS. Next, a comparison is performed between a list of the discovered PCIe device(s) and an expected list of PCIe devices for the ADS. Next, an offline PCIe device is determined based on the comparison, the offline PCIe device corresponding to a PCIe device that is present in the expected list of PCIe devices but not in the list of the discovered PCIe devices. Then a device reset command is transmitted to a programmable logic device that manages power for PCIe devices of the ADS to reset the offline PCIe device, wherein the programmable logic device generates a reset control signal for the offline PCIe device to reset the PCIe device.
    Type: Application
    Filed: January 20, 2023
    Publication date: March 13, 2025
    Inventors: Yun JI, Congshi HUANG, Zhenwei YU, Dongpo ZOU, Zhiyuan LI
  • Publication number: 20250087529
    Abstract: A method for filling a gap includes: filling a dielectric layer in the gap so that a seam is formed in the dielectric layer, the dielectric layer including two surface portions at two opposite sides of the seam, respectively; introducing a surface modification agent into the seam such that each of the two surface portions has first functional groups and second functional groups; forming a stress layer on the dielectric layer to cover the seam, the stress layer including a material different from that of the dielectric layer; and applying an energy field to permit the two surface portions to bond with each other through reaction between the first functional groups and the second functional groups.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsien CHENG, Tai-Chun HUANG, Chung-Ting KO, Chia-Yu FANG, Sung-En LIN, Yu-Yun PENG
  • Publication number: 20250085622
    Abstract: EUV masks and methods of fabrication thereof are described herein. An exemplary method includes receiving an EUV mask having a multilayer structure, a capping layer disposed over the multilayer structure, a patterned absorber layer disposed over the capping layer, and a patterned hard mask disposed over the patterned absorber layer. The method further includes removing the patterned hard mask by performing a first etching process to partially remove the patterned hard mask and performing a second etching process to remove a remainder of the patterned hard mask. The first etching process uses a first etchant, and the second etching process uses a second etchant. The second etchant is different than the first etchant. In some embodiments, the first etchant is a halogen-based plasma (e.g., a Cl2 plasma), and the second etchant is a halogen-and-oxygen-based plasma (e.g., a Cl2+O2 plasma).
    Type: Application
    Filed: January 18, 2024
    Publication date: March 13, 2025
    Inventors: Chun-Lang CHEN, Chung-Yang HUANG, Shih-Hao YANG, Chien-Yun HUANG, Wei-Ting CHEN
  • Publication number: 20250075096
    Abstract: The present disclosure discloses a preparation method for a transparent conductive polymer film, wherein the method comprises the following steps: (a) providing a precursor solution, wherein the precursor solution comprises a main solvent, an auxiliary solvent, an oxidizing agent and a thiophene monomer, wherein the auxiliary solvent comprises one or more of water, an aqueous solution containing hydrogen ions, a cyclic amide, a cyclic urea, a chain alkyl urea, phosphate or phosphoramide, and (b) coating the surface of a substrate with the precursor solution, so that the thiophene monomer is subjected to a polymerization reaction to form a conductive polymer film. The preparation method according to the present disclosure is economical, effective and simple, and the fabrication of high-quality transparent conductive polymer films by a one-step solution method has promising applications.
    Type: Application
    Filed: December 26, 2022
    Publication date: March 6, 2025
    Inventors: Sonigara K. KEVAL, Jingsong HUANG, Stavrinou PAUL, Donal D.C. BRADLEY, Yun HU, Dewan WANG
  • Publication number: 20250081523
    Abstract: A semiconductor die and the method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. The conductive feature contacts the shared contact.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: Chen-Ming Lee, Shih-Chieh Wu, Po-Yu Huang, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250075002
    Abstract: The present disclosure provides for multi-specific antibodies and antigen-binding fragments thereof that bind to human MUC1 and CD16A, pharmaceutical compositions comprising said antibodies, and use of the antibodies or the compositions for treating a disease, such as cancer.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 6, 2025
    Applicant: BeiGene Switzerland GmbH
    Inventors: Hui LI, Qiansheng REN, Liang QU, Ming JIANG, Qi LIU, Xin CHEN, Yun CHEN, Liu XUE, Wenjie WANG, Jie PAN, Zhuo LI, Xiaoyan TANG, Chichi HUANG, Ting SHAO
  • Patent number: 12240006
    Abstract: An all-plastic pump comprising an outer cover, a plastic spring, an inner cover and a pressing head. The pump includes an accessory cavity in the outer cover, with a conveying hole. A tubular plastic spring is positioned within the cavity, surrounding the conveying hole. Supporting rods are arranged circumferentially on an inner wall of the plastic spring's port, with one end of the rods connected to a baffle. The inner cover surrounds the plastic spring, and a stop tube is inserted through the supporting rods, with its port sealing against the baffle. The pressing head, mounted in a pressable manner, includes a discharging hole, pressing sheet, and conveying tube. When pressed, the pressing sheet compresses the plastic spring, causing separation between the baffle and stop tube, allowing fluid discharge.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: March 4, 2025
    Assignee: Guangzhou Shanggong Plastic Co., Ltd
    Inventors: Qiquan Liang, Yun Huang, Haoyu Liang
  • Patent number: 12244225
    Abstract: A flyback DC-DC converter. The converter having a transformer with a primary and a secondary windings, first and second switches, a capacitor coupled between the second switch and the primary winding, where the second switch is arranged to operate such that a sum of a first and second time periods equals a sum of third and fourth time periods, where the first time period is a delay time period from a time that the first switch is turned off to a time that the second switch is turned on, the second time period is a time period that the second switch is on, the third time period is a resonance time period of a resonator formed by a leakage inductance of the transformer and a capacitance of the capacitor, and the fourth time period is a time period for discharge of the leakage inductance of the transformer into the capacitor.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: March 4, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Xiucheng Huang, Bin Li, Weijing Du, Yun Zhou
  • Patent number: 12242108
    Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
  • Patent number: 12234522
    Abstract: A method for controlling carbide network in a bearing steel wire rod by controlling cooling and rolling, comprises the following steps: rapidly rolling a bar to a wire rod and spinning it into a loose coil, controlling the rolling temperature at 780° C.-880° C.; and the spinning temperature at 750° C.-850° C.; carrying out on-line controlling cooling of continuous loose coils using EDC water bath austempering cooling process, controlling the cooling rate at 2.0° C./s-10° C./s, and controlling the final cooling temperature within 620-630° C.; after EDC water bath austempering cooling, using slow cooling under a cover, and the temperature is controlled to be 400° C.-500° C. when being removed out of the cover; after slow cooling, collecting coils, and cooling in air to the room temperature.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 25, 2025
    Assignees: JIANGYIN XINGCHENG GOLD MATERIALS CO., LTD, JIANGYIN XINGCHENG SPECIAL STEEL WORKS CO., LTD
    Inventors: Lin Zhang, Jianfeng Zhang, Changhe Lu, Yuehui Guan, Guozhong Li, Xiaohong Xu, Yun Bai, Hao Zong, Jiafeng He, De Chen, Zhen Huang, Jia Yang