Abstract: An overdriving apparatus is provided in the invention. The apparatus includes a receiving module, a storing module, a dynamic information generating module, and an image driving module. The receiving module receives image data relative to an image signal. The storing module is used for storing the image data. Based on the image data, the dynamic information generating module generates dynamic information corresponding to a current image. The image driving module then generates an overdriving signal and/or a standard driving signal, according to the dynamic information and the image data, to drive a display.

Abstract: A circuit for overdriving an LCD panel according to an image data and a temperature, and the corresponding are disclosed. The circuit includes: a memory for storing a previous image data; a plurality of LUTs, each coupled to receive the previous image data from the memory and a present image data, for storing overdrive values; a first temperature sensor, for sensing the temperature of a first area of the LCD panel to generate a first temperature data; a control circuit, for generating a selection signal and a temperature correction coefficient according to the first temperature data; a selection circuit, coupled to the plurality of LUTs, for selecting one LUT from the plurality of LUTs according to the selection signal and outputting the overdrive value of the selected LUT; and an overdrive processor, for generating adjusted image data according to the overdrive value and the temperature correction coefficient.

Abstract: A dithering method includes: utilizing a plurality of large dithering masks to perform dithering on a first set of Least Significant Bits (LSBs) of M-bit video data, utilizing a plurality of small dithering masks to perform dithering on a second set of LSBs of the M-bit video data, and adjusting the content of at least one of the plurality of large dithering masks and/or the content of at least one of the plurality of small dithering masks on a frame-by-frame basis. Each of the plurality of large dithering masks includes a plurality of sub-dithering masks. Each of the plurality of sub-dithering masks includes a plurality of dithering thresholds. Each of the plurality of small dithering masks includes a plurality of dithering thresholds.

Abstract: A method for eliminating image blur, includes: performing motion detection on two successive images of a video signal to generate a motion index; and adjusting the luminance of the two successive images according to two transfer functions determined by the motion index, respectively.

Abstract: The present invention discloses a method for displaying video data. The method includes: generating an intermediate image between a first and a second image of the video data, wherein the first image is adjacent to the second image in the video data; adjusting a plurality of intermediate pixels of the intermediate image to generate a luminance-adjusted image; and displaying the first image, the luminance-adjusted image, and the second image in turn.

Abstract: A liquid crystal display (LCD) control circuit is disclosed. The control circuit includes an edge detecting circuit for detecting image edges in each frame of an image data, and outputting an edge data and a non-edge data; a memory for saving the edge data of the frame; a driving decision circuit for generating a driving voltage setting according to the non-edge data of a current frame, and generating an overdriving voltage setting according to the edge data of a previous frame saved in the memory and the edge data of the current frame outputted by the edge detecting circuit; and an output device for outputting the driving voltage setting and the overdriving voltage setting.

Abstract: The present invention provides a noise reduction method for use in reducing noise of a digital image, the method comprising steps of: providing at least a luminance threshold value; determining at least a luminance feature value according to the luminance value of a target pixel and the luminance values of neighboring pixels of the target pixel; determining whether the target pixel is a noise point based on the comparison between each luminance feature value and each luminance threshold value corresponding thereto; and adjusting the luminance value, a first chrominance value and a second chrominance value of the target pixel if the target pixel is determined a noise point. Using the noise reduction method of the present invention, not only noise of a digital image can be identified, but also the degradation caused by the noise can be reduced and thus the overall picture quality can be improved.

Abstract: The present invention provides a noise reduction method for use in reducing noise of a digital image, the method comprising steps of: defining a target window on a coordinate plane defined by the first chrominance and the second chrominance as the horizontal axis and the vertical axis; determining a noise threshold value according to whether an input pixel having a first chrominance value and a second chrominance value is located inside the window; determining whether the input pixel is a noise point according to the noise threshold value and luminance values of neighboring pixels of the input pixel; and adjusting the luminance value of the input pixel if the input pixel is determined a noise point. Using the noise reduction method of the present invention, not only noise of a digital image can be identified, but also the degradation caused by the noise can be reduced and thus the overall picture quality can be improved.

Abstract: A method of reducing fluorine contamination on a integrated circuit wafer surface is achieved. The method comprises placing an integrated circuit wafer on a cathode stage. The integrated circuit wafer comprises a surface contaminated with fluorine. The integrated circuit wafer is plasma treated with a plasma comprising a reducing gas that forms HF from the fluorine and a bombardment gas that removes the fluorine from the surface. The cathode stage is heated to thereby increase the rate of the fluorine removal.

Abstract: A process for fabricating a dual damascene structure of copper has been developed. This process uses a thin nitride spacer, approximately 100 Angstroms thick, at the bottom of the via, thus preventing recessed nitride during the resist stripping process.

Abstract: A method of reducing fluorine contamination on a integrated circuit wafer surface is achieved. The method comprises placing an integrated circuit wafer on a cathode stage. The integrated circuit wafer comprises a surface contaminated with fluorine. The integrated circuit wafer is plasma treated with a plasma comprising a reducing gas that forms HF from the fluorine and a bombardment gas that removes the fluorine from the surface. The cathode stage is heated to thereby increase the rate of the fluorine removal.

Abstract: A ESD-free container is provided. A compound material is used for the creation of the container, the compound material comprising a metallic material that is wedged between layer of polymide material. The compound material is surrounded by layers of PMMA, resulting in a container having a cavity that is surrounded by a first layer of PMMA, a second layer of the compound material and a third layer of PPMA.

Abstract: A new method is provided for monitoring silicon quality, the new method is applied at the time of pre-salicidation of the silicon substrate. The optical refractive index of the pre-salicide substrate is monitored, this monitoring provides insight into the quality of the silicon substrate at that time of a substrate processing cycle.

Abstract: An improved and new process for fabricating a dual damascene structure of copper has been developed. Conventional methods use silicon nitride as a protective liner of the dual damascene trench/via. However, problems arise with the conventional methods due to recessed nitride at the damascene bottom via area, which affects the performance of the subsequent copper fill, and makes for a noncontinuous barrier coating at the bottom of the via. This improved and new process uses a thin nitride spacer, approximately 100 Angstroms thick, at the bottom of the via, thus preventing recessed nitride during the resist stripping process.

Abstract: A method for forming within a dielectric layer upon a substrate within a microelectronics fabrication a series of contact via holes etched through the dielectric layer to multi-level contact layers employing reactive plasma etching methods to form the series of contact via holes. The first plasma etch method employs fluorine containing gases to form the etched via holes, and then the second plasma etch method employs oxygen and a fluorocarbon gas to complete the etching of the via holes and remove residual materials. The etched via holes access multi-level contact layers formed upon the substrate at differing heights with respect to the substrate, penetrating through at least one contact layer. This permits formation of a series of electrical contacts, between the series of contact layers and patterned conductor layers through the series of via holes, with low electrical resistances.

Abstract: A method for fabricating a polycide self aligned contact for MOSFET devices in which the electrical isolation between the source/drain contact and gate structure is improved. In the method a gate insulator layer, a polysilicon layer, a metal silicide layer and an insulating layer are deposited on a semiconductor substrate. The insulator layer is patterned and anisotropically etched to expose the underlying metal silicide layer. The metal silicide layer is then dip etched to form an undercut beneath the insulating layer. The metal silicide and polysilicon layers are patterned with an anisotropic etch, dopants introduced into the opening to form lightly doped source/drain regions, and sidewall spacers formed on the sidewalls of the etched layers. After a dopant is introduced to form heavily doped source/drain regions, a contact structure is formed in the opening defined by the sidewall spacers.

Abstract: A method for fabricating a polycide self aligned contact for MOSFET devices in which the electrical isolation between the source/drain contact and gate structure is improved. In the method a gate insulator layer, a polysilicon layer, a metal silicide layer and an insulating layer are deposited on a semiconductor substrate. The insulator layer is patterned and anisotropically etched to expose the underlying metal silicide layer. The metal silicide layer is then dip etched to form an undercut beneath the insulating layer. The metal silicide and polysilicon layers are patterned with an anisotropic etch, dopants introduced into the opening to form lightly doped source/drain regions, and sidewall spacers formed on the sidewalls of the etched layers. After a dopant is introduced to form heavily doped source/drain regions, a contact structure is formed in the opening defined by the sidewall spacers.

Abstract: A method for forming on a substrate employed within a microelectronics fabrication a planarized inter-level metal dielectric (IMD) layer employing spin-on-glass (SOG) dielectric material, with attenuated etching damage to underlying layers. There is provided a substrate upon which is formed a patterned microelectronics layer over which is formed an inter-level metal dielectric (IMD) layer comprising a first silicon oxide dielectric layer and a second spin-on-glass (SOG) dielectric layer. The IMD layer is then planarized by plasma etchback method employing an etch cycle interrupted by an inert gas flushing step and substrate backside cooling by helium gas to control substrate temperature and etching reaction rates, resulting in attenuated damage to underlying layers resulting from over-etching of the IMD layer.

Abstract: A process for forming a self-aligned contact, (SAC), structure, on an active device region in a semiconductor substrate, exposed at the bottom of a SAC opening in an insulator layer, has been developed. The process features increasing the area of the active device region, used to accommodate the overlying SAC structure, via the selective removal of the thick spacer component, of a composite spacer, located on the sides of silicon nitride capped, gate structures, performed after definition of a heavily doped source/drain region. The thick spacer component can be a polysilicon shape overlying a thin silicon oxide shape, or the thick spacer component can be a silicon oxide shape, overlying a silicon nitride shape.

Abstract: A photoresist stripper bath includes a filter in a re-circulation line for filtering residual photoresist materials from said bath. The quality of the stripper and the concentration of the photoresist materials are sensed by passing infrared light transversely through the re-circulating line, detecting the intensity of the light passed through the line and comparing the detected level with a threshold value related to the concentration of the photoresist materials in said stripper.