Patents by Inventor Yun Jing

Yun Jing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190123198
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 10164093
    Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Publication number: 20180307782
    Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.
    Type: Application
    Filed: March 22, 2018
    Publication date: October 25, 2018
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao, Chien-Nan Liu, Yu-Kang Lou, Ching-Ho Lin
  • Publication number: 20170186867
    Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 9595477
    Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: March 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 9153655
    Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
  • Patent number: 9111906
    Abstract: The present disclosure describes a method of fabricating semiconductor device including providing a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is formed on the substrate abutting the first gate stack. In an embodiment, a source/drain region is then formed. A second spacer element is then formed is adjacent the first spacer element. The second spacer element has a second height from the surface of the substrate, and the first height is greater than the second height. In embodiments, the second spacer element is used as an etch stop in forming a contact to the source/drain region.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
  • Publication number: 20140291768
    Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.
    Type: Application
    Filed: May 20, 2014
    Publication date: October 2, 2014
    Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
  • Publication number: 20140246728
    Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.
    Type: Application
    Filed: May 20, 2014
    Publication date: September 4, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
  • Publication number: 20140248752
    Abstract: The present disclosure describes a method of fabricating semiconductor device including providing a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is formed on the substrate abutting the first gate stack. In an embodiment, a source/drain region is then formed. A second spacer element is then formed is adjacent the first spacer element. The second spacer element has a second height from the surface of the substrate, and the first height is greater than the second height. In embodiments, the second spacer element is used as an etch stop in forming a contact to the source/drain region.
    Type: Application
    Filed: May 20, 2014
    Publication date: September 4, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
  • Patent number: 8735988
    Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
  • Publication number: 20130290574
    Abstract: A keyboard for an electronic device includes a main body, a connection state indicator positioned on an outside surface of the main body, and a keyboard port. Both the main body and the connection state indicator are electrically connected to a network host of an electronic device through the keyboard port. The electronic device can be operated using the keyboard and the connection state indicator indicates a connection state between the network host and a local area network.
    Type: Application
    Filed: October 25, 2012
    Publication date: October 31, 2013
    Inventors: YUN-JING WANG, CAI-JIN YUAN
  • Patent number: 8455952
    Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: June 4, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
  • Publication number: 20120187459
    Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 8220368
    Abstract: A screwdriver is convenient for changing various heads. The heads can be easily detached from the screwdriver, and mounted to the screwdriver.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: July 17, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Yun-Jing Chen
  • Publication number: 20120126331
    Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
  • Patent number: 8100042
    Abstract: An adhesive tape canister includes a reel to mount a roll of adhesive tape. When the adhesive tape needs to be cut, a handle portion of the adhesive tape canister is pressed, a first blade is moved towards the second blade. The adhesive tape can be cut by the first blade and the second blade in response to the first blade moving to the second blade.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: January 24, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Yun-Jing Chen
  • Publication number: 20110036503
    Abstract: An adhesive tape canister includes a reel to mount a roll of adhesive tape. When the adhesive tape needs to be cut, a handle portion of the adhesive tape canister is pressed, a first blade is moved towards the second blade. The adhesive tape can be cut by the first blade and the second blade in response to the first blade moving to the second blade.
    Type: Application
    Filed: August 27, 2009
    Publication date: February 17, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: YUN-JING CHEN
  • Publication number: 20110000346
    Abstract: A screwdriver is convenient for changing various heads. The heads can be easily detached from the screwdriver, and mounted to the screwdriver.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 6, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: YUN-JING CHEN
  • Publication number: 20100118705
    Abstract: A method includes receiving a request from a mobile station (102) to initiate a call session with a base station (104). After receiving the request, the base station determines that it cannot process the call session with the mobile station because the base station is fully loaded and sends a busy indication to the mobile station in response to determining that it cannot process the call session. The method can also include sending a scan response to the mobile station indicating a load for a neighboring base station (106) to the base station and handing over the mobile station to the neighboring base station.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 13, 2010
    Applicant: MOTOROLA, INC.
    Inventors: Vikas Mehrotra, Rishi R. Arora, Yun Jing, Apurv Mathur