Patents by Inventor Yun Ling Tan
Yun Ling Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11742283Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes a memory device in back end of line (BEOL) materials and a thin film resistor located in the BEOL materials. The thin film resistor includes electrical resistive material, and an insulator material over the electrical resistive material is thicker than insulator material over the memory device.Type: GrantFiled: December 31, 2020Date of Patent: August 29, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Kah Wee Gan, Benfu Lin, Yun Ling Tan
-
Patent number: 11610837Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.Type: GrantFiled: September 21, 2020Date of Patent: March 21, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xuesong Rao, Benfu Lin, Bo Li, Chengang Feng, Yudi Setiawan, Yun Ling Tan
-
Publication number: 20220208675Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes: a memory device in back end of line (BEOL) materials; and a thin film resistor located in the BEOL materials.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Kah Wee GAN, Benfu LIN, Yun Ling TAN
-
Patent number: 11315876Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.Type: GrantFiled: February 17, 2020Date of Patent: April 26, 2022Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Xuesong Rao, Yun Ling Tan, Yudi Setiawan, Siow Lee Chwa
-
Publication number: 20220093508Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.Type: ApplicationFiled: September 21, 2020Publication date: March 24, 2022Inventors: XUESONG RAO, BENFU LIN, BO LI, CHENGANG FENG, YUDI SETIAWAN, YUN LING TAN
-
Publication number: 20210257300Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.Type: ApplicationFiled: February 17, 2020Publication date: August 19, 2021Inventors: XUESONG RAO, YUN LING TAN, YUDI SETIAWAN, SIOW LEE CHWA
-
Patent number: 10784332Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.Type: GrantFiled: March 22, 2018Date of Patent: September 22, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Liang Li, Yun Ling Tan, Kai Hung Alex See, Lulu Peng, Donald Ray Disney
-
Patent number: 10566441Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.Type: GrantFiled: February 14, 2018Date of Patent: February 18, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Hao Nong, Liang Li, Chiew Wah Yap, Ting Huo, Yung Fu Chong, Yun Ling Tan
-
Publication number: 20190296100Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.Type: ApplicationFiled: March 22, 2018Publication date: September 26, 2019Inventors: Liang Li, Yun Ling Tan, Kai Hung Alex See, Lulu Peng, Donald Ray Disney
-
Patent number: 10410854Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.Type: GrantFiled: December 28, 2017Date of Patent: September 10, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Honghui Mou, Xiaodong Li, Yun Ling Tan, Alex See, Liang Li
-
Publication number: 20190252515Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.Type: ApplicationFiled: February 14, 2018Publication date: August 15, 2019Inventors: Hao Nong, Liang Li, Chiew Wah Yap, Ting Huo, Yung Fu Chong, Yun Ling Tan
-
Publication number: 20190206676Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Honghui MOU, Xiaodong LI, Yun Ling TAN, Alex SEE, Liang LI
-
Patent number: 10115625Abstract: Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.Type: GrantFiled: December 30, 2016Date of Patent: October 30, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Liang Li, Yun Ling Tan, Hai Cong, Changwei Pei, Alex See
-
Publication number: 20180190537Abstract: Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Liang LI, Yun Ling TAN, Hai CONG, Changwei PEI, Alex SEE
-
Patent number: 9548371Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.Type: GrantFiled: April 23, 2014Date of Patent: January 17, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Jingyan Huang, Chuan Wang, Chim Seng Seet, Yun Ling Tan, Alex See
-
Patent number: 9230886Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: GrantFiled: December 18, 2014Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
-
Publication number: 20150311221Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.Type: ApplicationFiled: April 23, 2014Publication date: October 29, 2015Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jingyan Huang, Chuan Wang, Chim Seng Seet, Yun Ling Tan, Alex See
-
Publication number: 20150137359Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: ApplicationFiled: December 18, 2014Publication date: May 21, 2015Inventors: Lup San LEONG, Zheng ZOU, Alex Kai Hung SEE, Hai CONG, Xuesong RAO, Yun Ling TAN, Huang LIU
-
Patent number: 8940637Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: GrantFiled: July 5, 2012Date of Patent: January 27, 2015Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
-
Patent number: 8860142Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.Type: GrantFiled: October 10, 2012Date of Patent: October 14, 2014Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Debora Chyiu Hyia Poon, Alex K H See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia