Patents by Inventor Yun Ling Tan
Yun Ling Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8853796Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.Type: GrantFiled: May 19, 2011Date of Patent: October 7, 2014Assignees: GLOBALFOUNDIERS Singapore Pte. Ltd.Inventors: Young Way Teh, Michael V. Aquilino, Arifuzzaman (Arif) Sheikh, Yun Ling Tan, Hao Zhang, Deleep R. Nair, Jinghong H. (John) Li
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Patent number: 8828858Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.Type: GrantFiled: January 19, 2012Date of Patent: September 9, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
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Publication number: 20140008810Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: ApplicationFiled: July 5, 2012Publication date: January 9, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
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Publication number: 20130187202Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
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Patent number: 8492236Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.Type: GrantFiled: January 12, 2012Date of Patent: July 23, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
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Publication number: 20130181259Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
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Publication number: 20120292719Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.Type: ApplicationFiled: May 19, 2011Publication date: November 22, 2012Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Young Way TEH, Michael V. AQUILINO, Arifuzzaman (Arif) SHEIKH, Yun Ling TAN, Hao ZHANG, Deleep R. NAIR, Jinghong H. (John) LI
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Patent number: 8293544Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.Type: GrantFiled: July 28, 2008Date of Patent: October 23, 2012Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Debora Chyiu Hyia Poon, Alex Kh See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
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Publication number: 20100019329Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.Type: ApplicationFiled: July 28, 2008Publication date: January 28, 2010Inventors: Debora Chyiu Hyia Poon, Alex KH See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
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Publication number: 20080087958Abstract: A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: ApplicationFiled: December 6, 2007Publication date: April 17, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Purakh Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Patent number: 7326609Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: GrantFiled: May 6, 2005Date of Patent: February 5, 2008Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Purakh Raj Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Patent number: 7176094Abstract: DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.Type: GrantFiled: March 6, 2002Date of Patent: February 13, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Dong Zhong, Yun Ling Tan, Chew Hoe Ang, Jia Zhen Zheng
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Publication number: 20060252188Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: ApplicationFiled: May 6, 2005Publication date: November 9, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Purakh Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Publication number: 20030170956Abstract: DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.Type: ApplicationFiled: March 6, 2002Publication date: September 11, 2003Applicant: Chartered Semiconductor manufacturing Ltd.Inventors: Dong Zhong, Yun Ling Tan, Chew Hoe Ang, Jia Zhen Zheng