Patents by Inventor Yun Peng
Yun Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240145579Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Yun PENG, Fu-Ting YEN, Keng-Chu LIN
-
Patent number: 11972974Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.Type: GrantFiled: January 13, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
-
Publication number: 20240136438Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.Type: ApplicationFiled: December 22, 2023Publication date: April 25, 2024Inventors: Yu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
-
Publication number: 20240113250Abstract: The present disclosure discloses a continuous string welding device for photovoltaic cells and a welding method. The device includes a power transmission mechanism and a welding light box. The power transmission mechanism includes a welding strip positioning section, a buffering section and a welding section that perform conveying independently from each other in sequence in the conveying direction. The buffering section is capable of storing at least one string of cells. The welding light box is located in the welding section. The welding strip positioning section performs step-by-step motion conveying. The welding section performs continuous motion conveying. The buffering section is configured to receive a predetermined number of cells from the welding strip positioning section, connect the predetermined number of cells in series, and then convey the predetermined number of cells connected in series to the welding section.Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Applicant: TRINA SOLAR CO., LTD.Inventors: Zhiqiang DING, Junlong HU, Hao TANG, Yun PENG
-
Patent number: 11942358Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.Type: GrantFiled: March 12, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
-
Patent number: 11942447Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.Type: GrantFiled: August 27, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: De-Yang Chiou, Fu-Ting Yen, Yu-Yun Peng, Keng-Chu Lin
-
Patent number: 11935752Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.Type: GrantFiled: March 12, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yun Peng, Chung-Chi Ko, Keng-Chu Lin
-
Publication number: 20240081122Abstract: A display system may include a light source that emits input light having a wavelength within a source wavelength range and an array of color conversion units overlapping a display area. A first set of color conversion units of the array of color conversion units may include a first color conversion medium that converts the input light to a first color of light having a wavelength within a first wavelength range that is different than the source wavelength range. The display system may also include a waveguide having an out-coupler that directs the input light from the light source toward the array of color conversion units. Various other devices, systems, and methods are also disclosed.Type: ApplicationFiled: September 7, 2023Publication date: March 7, 2024Inventors: Zhimin Shi, Yun Wang, Fenglin Peng, Christophe Antoine Hurni, James Ronald Bonar, Edward Buckley, Andrew John Ouderkirk, Yongdan Hu
-
Patent number: 11912867Abstract: Described herein is a polyurethane having an isocyanate group and having C—C double bonds on a side chain, a process for preparing such a polyurethane, and an UV-moisture dual cure polyurethane reactive hotmelt including the polyurethane.Type: GrantFiled: January 14, 2020Date of Patent: February 27, 2024Assignee: BASF SEInventors: Xuyuan Peng-Poehler, Yun Fei Guo, Li Chen
-
Patent number: 11908921Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.Type: GrantFiled: August 26, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Yun Peng, Fu-Ting Yen, Keng-Chu Lin
-
Patent number: 11899048Abstract: A voltage state detector includes a voltage drop circuit, a pull-down circuit, a load circuit, a transistor, a pull-up circuit, first and second output terminals, and a logic circuit. The pull-down circuit is coupled to the voltage drop circuit. The transistor has a first terminal coupled to the load circuit, a second terminal coupled to the pull-down circuit, and a control terminal coupled to the voltage drop circuit. The pull-up circuit is coupled to the load circuit and the voltage drop circuit. The first output terminal is coupled to the first terminal of the transistor for outputting a first state determination signal. The second output terminal is coupled to the voltage drop circuit for outputting a second state determination signal. The logic circuit includes a NOR gate for performing an NOR operation on the first state determination signal and the second state determination signal to output a control signal.Type: GrantFiled: February 16, 2023Date of Patent: February 13, 2024Assignee: RichWave Technology Corp.Inventors: Tien-Yun Peng, Hsien-Huang Tsai, Chih-Sheng Chen
-
Publication number: 20240030180Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Yong LIANG, Wei-Ting YEH, Yu-Yun PENG, Keng-Chu LIN
-
Publication number: 20240008444Abstract: An absorbent article for pet excreta includes a liquid-permeable topsheet layer, a liquid-permeable backsheet layer, and a liquid-absorbing unit. The liquid-permeable backsheet layer is disposed spaced apart from the liquid-permeable topsheet layer. The liquid-absorbing unit is disposed between the liquid-permeable topsheet layer and the liquid-permeable backsheet layer, and is adapted for absorbing pet excreta from at least one of the liquid-permeable topsheet layer and the liquid-permeable backsheet layer.Type: ApplicationFiled: December 15, 2022Publication date: January 11, 2024Inventors: Chien-Chung SU, Yu-Hsuan TSENG, Yun-Peng LIU
-
Patent number: 11854796Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The structure also includes a sealing element extending along a sidewall of the gate stack. The sealing element has a first atomic layer and a second atomic layer, and the first atomic layer and the second atomic layer have different atomic concentrations of carbon. The structure further includes a spacer element over the sealing element.Type: GrantFiled: June 29, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Guan-Yao Tu, Yu-Yun Peng
-
Patent number: 11855214Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.Type: GrantFiled: March 15, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.Inventors: Yu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
-
Publication number: 20230395683Abstract: A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuei-Lin CHAN, Fu-Ting YEN, Yu-Yun PENG, Keng-Chu LIN
-
Patent number: 11837515Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.Type: GrantFiled: April 26, 2021Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yin-Jie Pan, Yu-Yun Peng
-
Publication number: 20230386947Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Yin-Jie Pan, Yu-Yun Peng
-
Publication number: 20230387254Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith KHADERBAD, Keng-Chu LIN, Yu-Yun PENG
-
Publication number: 20230387065Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: De-Yang CHIOU, Yu-Yun Peng, Fu-Ting Yen, Keng-Chu Lin