Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer and performing an oxide refill process to form a seamless dielectric material between the second and third semiconductor layers. The oxide refill process includes exposing the second and third semiconductor layers to a silicon-containing precursor at a first flow rate for a first duration to form a monolayer, and exposing the monolayer to an oxygen-containing precursor at a second flow rate for a second duration to form the seamless dielectric material, the second flow rate is about twice to about 20 times the first flow rate, and the second duration is about twice to about 20 times the first duration.

Abstract: The present invention provides a method for impact analysis of port construction on a coastal ecotone based on remote sensing data, which belongs to the technical field of remote sensing application. The method quantifies landscape data and satellite image data, and then converts the data into intuitive images to observe the spatio-temporal change of the coastal ecotone after port construction. The method includes: step 1: obtaining remote sensing image data of a research region; step 2: preprocessing the remote sensing image data to obtain processed images; step 3: establishing an evaluation system of human disturbance indexes; and step 4: generating a spatio-temporal distribution map of regional disturbance indexes. The present invention provides a method capable of quantifying the impact range and the impact degree of the port construction factor on the coastal ecotone, provides an idea for reducing the impact of port construction on a surrounding environment.

Abstract: A method of dust pollution monitoring and risk forewarning for a dry bulk port based on an inspection robot belongs to the technical field of environmental monitoring. The method plans an inspection route of the inspection robot in the stage of the inspection robot path planning, and makes the inspection robot perform an inspection task automatically along the planned route; in the stage of data acquisition, transmission, and processing, a multi-source environmental monitoring module installed on the inspection robot is used for monitoring the concentration of dust pollutants in the air and environmental parameters in real-time; and in the stage of data analysis and risk forewarning, the monitoring data is analyzed and visualized to judge a possible over-standard risk of dust pollutant concentration and perform forewarning. The present invention can improve the resolution and flexibility of dust pollution monitoring in the dry bulk port.

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

Abstract: An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.

Abstract: A switch device includes a driver circuit, a switch circuit and a level transition circuit. The driver circuit includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first terminal coupled to a first reference terminal, and a second terminal coupled to a second reference terminal. The switch circuit includes a control terminal for receiving the output signal. The level transition circuit includes a first terminal for receiving the output signal, a second terminal coupled to a third reference terminal, and a third terminal for receiving the input signal. In a transition interval, the input signal is transitioned from a first input signal level to a second input signal level, the level transition circuit transitions the output signal from a first output signal level to a third output signal level between the first output signal level and a second output signal level.

Abstract: A bias circuit includes a current mirror circuit, an operational amplifier, and a bias generating circuit. The current mirror circuit includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to a base current, and the at least one mirror branch circuit generates at least one mirrored current according to the reference current. The operational amplifier receives a first voltage from the reference branch circuit and a second voltage from the at least one mirror branch circuit, and adjusts the first voltage by generating a control voltage according to the second voltage. The bias generating circuit is coupled to the at least one mirror branch circuit and generates a bias signal according to the at least one mirrored current.

Abstract: The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.

Abstract: A method for forming an interconnect structure is provided. The method includes the following operations. A contact is formed over a substrate. An interlayer dielectric (ILD) layer is formed over the contact and the substrate. An opening is formed in the ILD layer thereby exposing a portion of the contact. A densified dielectric layer is formed at an exposed surface of the ILD layer by the opening and an oxide layer over the portion of the contact by irradiating a microwave on the exposed surface of the ILD layer.

Abstract: A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

Abstract: A semiconductor device includes a substrate, a first active structure, a second active structure, a wall and a STI layer. The first active structure is formed on the substrate. The second active structure is formed on the substrate. The wall is formed between the first active structure and the second active structure. The STI layer is formed adjacent to the first active structure and has an upper surface. A distance between a spacer of the first active structure and the upper surface of the STI layer may range between 0 and 50 nanometers.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.

Abstract: Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

Abstract: A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.

Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

Abstract: A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

Abstract: A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.

Abstract: An interconnect structure, along with methods of forming such, are described. In some embodiments, the structure includes a first dielectric layer disposed over one or more devices, a first conductive feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first conductive feature, and a second conductive feature disposed in the second dielectric layer. The second conductive feature is electrically connected to the first conductive feature. The structure further includes a heat dissipation layer disposed between the first and second dielectric layers, and the heat dissipation layer partially surrounds the second conductive feature and is electrically isolated from the first and second conductive features.