Patents by Inventor Yun QIAO

Yun QIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210142747
    Abstract: An array substrate, a display panel, a display device, and driving methods thereof are provided. The array substrate includes subpixels arranged in an array, and switches. The subpixels include subpixels of a first color, subpixels of a second color, subpixels of a third color, subpixels of a fourth color, in odd rows of subpixels, the subpixels of the first color, the subpixels of the second color, the subpixels of the third color, the subpixels of the fourth color are sequentially arranged; in even rows of subpixels, the subpixels of the third color, the subpixels of the fourth color, the subpixels of the first color, the subpixels of the second color are sequentially arranged; and the subpixels of the first color are white subpixels; the subpixels of the second color are blue subpixels; the subpixels of the third color are green subpixels; the subpixels of the fourth color are red subpixels.
    Type: Application
    Filed: January 20, 2021
    Publication date: May 13, 2021
    Inventors: Zhen WANG, Wenwen QIN, Mingchao MA, Wenchao HAN, Jian SUN, Yun QIAO, Jun FAN
  • Patent number: 10996529
    Abstract: An array substrate includes plural sub-pixels in plural rows and plural columns; plural data ports; Ndl data lines, each of the Ndl data lines connecting to a column of sub-pixels, the Ndl data lines being divided into plural groups, each group including N data lines; and a multiplexer including M control lines and plural switching units in one-to-one correspondence with the Ndl data lines, each control line being connected to and controlling Ndl M switching units. All of the N data lines in each group are connected to one data port through N switching units, respectively, the data lines in different groups are connected to different data ports, the N switching units corresponding to each group are controlled by N different control lines, respectively, and at least two of the N data lines in each group are provided with a data line another group therebetween.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 4, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yun Qiao, Zhen Wang, Wei Wang, Fei Huang, Han Zhang, Peng Liu
  • Patent number: 10989947
    Abstract: Disclosed are an array substrate, a liquid crystal display panel and a display apparatus. The array substrate comprises a plurality of pixel units, with each of which being provided with a plurality of sub-pixels (R, G, B) arranged in a first direction; a plurality of touch control electrodes, a region where each of the touch control electrodes is located overlapping with a region where the plurality of sub-pixels (R, G, B) are located; and a plurality of touch control signal lines arranged in gaps between the sub-pixels (R, G, B), wherein each of the touch control signal lines is connected to each of the touch control electrodes, there is no touch control floating signal line not connected to each of the touch control electrodes, and one column of pixel units is correspondingly provided with one touch control signal line.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 27, 2021
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yun Qiao, Zhen Wang, Fei Huang, Xiaozhou Zhan, Han Zhang, Wenwen Qin, Jian Sun
  • Patent number: 10983630
    Abstract: A touch array baseplate panel, including a substrate and a film layer structure. The film layer structure includes: a touch electrode layer, including a plurality of touch electrodes arranged in an array; a first electrically conductive layer, including a plurality of touch electrode lines and virtual touch electrode lines; a second electrically conductive layer, including connection lines. A touch electrode line is electrically connected to a corresponding touch electrode through a first via hole, and a virtual touch electrode line is electrically connected to a corresponding touch electrode through a second via hole, and a connection line electrically connects, through third via holes, a touch electrode line and a virtual touch electrode line electrically connected to a same touch electrode. This disclosure further provides a method for manufacturing the touch array baseplate panel and a touch panel including the touch array baseplate panel.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 20, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenwen Qin, Jian Sun, Yun Qiao, Xiaozhou Zhan, Han Zhang, Zhen Wang, Lele Cong, Zhengkui Wang
  • Patent number: 10943554
    Abstract: A shift register unit, a method of driving a shift register unit, a gate driving circuit and a touch display device are disclosed. The shift register unit includes a first signal input terminal, a first voltage control terminal, a second signal input terminal, a second voltage control terminal, a signal output terminal, a first voltage terminal, and a second voltage terminal. The shift register unit further comprises a first input circuit, a second input circuit, an output circuit, an anti-leakage circuit, a first control circuit, and a second control circuit. The anti-leakage circuit is configured to bring a first node into conduction with a second node in response to an active potential of the second voltage terminal.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Zhen Wang, Jian Sun, Fei Huang, Yun Qiao, Xiaozhou Zhan, Han Zhang, Wenwen Qin, Lele Cong, Zhengkui Wang, Jianjun Zhang, Peng Liu
  • Patent number: 10936139
    Abstract: A touch panel including a substrate, an insulating layer, touch electrode blocks, and electrode lines. The touch electrode blocks include an array of first type touch electrode blocks having a regular shape and a second type touch electrode block having an irregular shape. Ones of the first type touch electrode blocks are electrically connected to respective ones of the electrode lines by respective X first contact vias extending through the insulating layer, and the respective X first contact vias are arranged along a straight line in a column direction. The second type touch electrode block is electrically connected to a first corresponding one of the electrode lines by Y second contact vias extending through the insulating layer, and the Y second contact vias are arranged along at least one straight line in the column direction. X and Y are natural numbers, and 0.75×X?Y?1.25×X.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 2, 2021
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Zhen Wang, Xiaozhou Zhan, Lele Cong, Yun Qiao, Jian Sun, Han Zhang, Wenwen Qin, Zhengkui Wang
  • Patent number: 10930360
    Abstract: A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: February 23, 2021
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Peng Liu, Jun Fan, Yusheng Liu, Bailing Liu, Han Zhang, Zhen Wang, Yun Qiao, Zhengkui Wang, Lele Cong, Mei Li
  • Patent number: 10923054
    Abstract: An array substrate, a display panel, a display device, and driving methods thereof are provided. The array substrate includes a plurality of subpixels arranged in an array, a plurality of data lines, and a plurality of switches. The plurality of subpixels include subpixels of a first color, subpixels of a second color, subpixels of a third color, and subpixels of a fourth color, in odd rows of subpixels, the subpixels of the first color, the subpixels of the second color, the subpixels of the third color, and the subpixels of the fourth color are sequentially arranged; in even rows of subpixels, the subpixels of the third color, the subpixels of the fourth color, the subpixels of the first color, and the subpixels of the second color are sequentially arranged; and each column of subpixels corresponds to and is connected with a data line.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 16, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Wang, Wenwen Qin, Mingchao Ma, Wenchao Han, Jian Sun, Yun Qiao, Jun Fan
  • Patent number: 10923206
    Abstract: The embodiments of the present disclosure relate to a shift registers unit and a driving method thereof, and a gate driving device. The shift register unit includes a first and second input circuit, a pull-down control circuit, an output circuit, a pull-down circuit, and a control circuit. The first input circuit provides a first control signal to a pull-up node. The second input circuit provides a second control signal to the pull-up node. The pull-down control circuit provides the voltage of a first voltage terminal to a pull-down node, or controls the voltage of the pull-down node. The output circuit provides a second clock signal to a signal output terminal. The pull-down circuit provides the voltage of the first voltage terminal to the pull-up node and the signal output terminal. The control circuit provides the first input signal to the pull-up node.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: February 16, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Zhen Wang, Jian Sun, Yun Qiao, Xiaozhou Zhan, Fei Huang, Han Zhang, Wenwen Qin, Lele Cong, Zhengkui Wang
  • Publication number: 20210026179
    Abstract: Disclosed are an array substrate, a liquid crystal display panel and a display apparatus. The array substrate comprises a plurality of pixel units, with each of which being provided with a plurality of sub-pixels (R, G, B) arranged in a first direction; a plurality of touch control electrodes, a region where each of the touch control electrodes is located overlapping with a region where the plurality of sub-pixels (R, G, B) are located; and a plurality of touch control signal lines arranged in gaps between the sub-pixels (R, G, B), wherein each of the touch control signal lines is connected to each of the touch control electrodes, there is no touch control floating signal line not connected to each of the touch control electrodes, and one column of pixel units is correspondingly provided with one touch control signal line.
    Type: Application
    Filed: May 23, 2018
    Publication date: January 28, 2021
    Inventors: Yun QIAO, Zhen WANG, Fei HUANG, Xiaozhou ZHAN, Han ZHANG, Wenwen QIN, Jian SUN
  • Patent number: 10902930
    Abstract: A shift register includes a first input sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit. The first input sub-circuit is configured to transmit a voltage from the first signal terminal to the first node under control of the first voltage terminal. The pull-up control sub-circuit is configured to be in a turn-on or turn-off state under control of the first node. The pull-down control sub-circuit is configured to transmit a voltage from the third voltage terminal to the pull-down node under control of the first node, transmit the voltage from the third voltage terminal to the pull-down node under control of the signal output terminal, and transmit a voltage from the first clock signal terminal to the pull-down node under control of the first clock signal terminal.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 26, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Peng Liu, Zhen Wang, Han Zhang, Kai Zhang, Yun Qiao, Jian Sun, Bailing Liu, Fei Huang, Zhengkui Wang, Jianjun Zhang
  • Publication number: 20210016096
    Abstract: Methods and systems are provided herein and include an HIS electrode configured to be located proximate to a HIS bundle and to at least partially define a HIS sensing channel. The system includes memory to store cardiac activity (CA) signals obtained over the HIS sensing channel, the memory to store program instructions; and one or more processors that, when executing the program instructions, are configured for utilizing an atrial oversensing (AO) process to analyze the CA signals, obtained over the HIS sensing channel during an AO avoidance (AOA) window, for an atrial activity (AA) component to identify AA beats. The system applies a consistency criteria to the AA beats to determine a number of the AA beats that are indicative of consistent AO. Based on the consistency criteria and the number of AA beats indicative of consistent AO, the system performs at least one of adjusting an AO parameter utilized by the AO process or disabling the AO process and manages HIS bundle pacing based on a ventricular event.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 21, 2021
    Inventors: Yun Qiao, Wenwen Li, Jan O. Mangual-Soto, Luke C. McSpadden
  • Publication number: 20210016097
    Abstract: Methods and systems for dynamically modifying pacing timing and backup pacing delivery in cardiac stimulation devices include applying pacing impulses, measuring corresponding responses, and, based on such responses, automatically modifying timing or operational settings of the stimulation device to improve pacing functionality. Among other things, the approaches described herein reduce unnecessary backup pacing impulses in HIS bundle pacing applications, facilitate fusion in bundle branch block applications, and automatically enable or disable backup pacing in response to achieving QRS complex correction.
    Type: Application
    Filed: May 11, 2020
    Publication date: January 21, 2021
    Inventors: Jan O. Mangual-Soto, John Yun Qiao, Wenwen Li, Xiaoyi Min, Luke C. McSpadden
  • Publication number: 20200356203
    Abstract: A shift register unit, a method of driving a shift register unit, a gate driving circuit and a touch display device are disclosed. The shift register unit includes a first signal input terminal, a first voltage control terminal, a second signal input terminal, a second voltage control terminal, a signal output terminal, a first voltage terminal, and a second voltage terminal. The shift register unit further comprises a first input circuit, a second input circuit, an output circuit, an anti-leakage circuit, a first control circuit, and a second control circuit. The anti-leakage circuit is configured to bring a first node into conduction with a second node in response to an active potential of the second voltage terminal.
    Type: Application
    Filed: December 11, 2018
    Publication date: November 12, 2020
    Inventors: Zhen WANG, Jian SUN, Fei HUANG, Yun QIAO, Xiaozhou ZHAN, Han ZHANG, Wenwen QIN, Lele CONG, Zhengkui WANG, Jianjun ZHANG, Peng LIU
  • Publication number: 20200353266
    Abstract: Systems and methods for His bundle pacing and classifying response to pacing impulses include applying, using a pulse generator, an impulse through a stimulating electrode to induce a response from a patient heart. A response to the impulse is measured using at least one sensing electrode and time-domain based characteristics of the response are analyzed to determine whether His bundle capture has occurred and, if so, what type of capture has occurred.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 12, 2020
    Applicant: Pacesetter, Inc.
    Inventors: Xiaoyi Min, Yun Qiao, Wenwen Li, Jan O. Mangual-Soto, Luke C. McSpadden
  • Publication number: 20200353249
    Abstract: Systems and methods for His bundle pacing and classifying response to pacing impulses include applying, using a pulse generator, an impulse through a stimulating electrode to induce a response from a patient heart. A response to the impulse is measured using at least one sensing electrode and frequency characteristics of the response are analyzed to determine whether His bundle capture has occurred and, if so, what type of capture has occurred. To facilitate analysis, the response measured from the patient heart may also be filtered to pass or stop frequencies indicative of certain capture types.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 12, 2020
    Applicant: Pacesetter, Inc.
    Inventors: Xiaoyi Min, Yun Qiao, Wenwen Li, Jan O. Mangual-Soto, Luke C. McSpadden
  • Patent number: 10825397
    Abstract: The present disclosure relates to a shift register unit. The shift register unit includes a first input circuit configured to transmit a first voltage signal to a pull-up node, a pull-up circuit configured to transmit a first clock signal to a signal output terminal, a first pull-down control circuit configured to transmit a second clock signal to a pull-down node, a second pull-down control circuit configured to transmit a second voltage signal to the pull-down node, a pull-up control circuit configured to transmit the second voltage signal to the pull-up node, a pull-down circuit configured to transmit the second voltage signal to the signal output terminal, and a holding circuit configured to maintain the pull-up node at a low level and/or maintain the pull-down node at a high level under control of a second input.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: November 3, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Wenwen Qin, Zhen Wang, Jian Sun, Xiaozhou Zhan, Jiguo Wang, Yun Qiao, Fei Huang, Han Zhang, Zhengkui Wang, Lele Cong
  • Patent number: 10795231
    Abstract: The present disclosure discloses an array substrate and its manufacturing method, a display panel and its manufacturing method, and a display device. The array substrate includes: a base substrate; a plurality of data lines; and a plurality of pixel units arranged on the base substrate, where each of the plurality of pixel units includes a plurality of subpixel units, and the plurality of subpixel units is in a one-to-one correspondence with the plurality of data lines, where each of the plurality of subpixel units includes a first subpixel unit and a second subpixel unit that are adjacently arranged, and the data line corresponding to the first subpixel unit and the data line corresponding to the second subpixel unit are both arranged at a position corresponding to a boundary between the first subpixel unit and the second subpixel unit.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 6, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Zhengkui Wang, Jian Sun, Yun Qiao, Han Zhang, Zhen Wang, Ruichao Liu, Jianjun Zhang, Peng Liu
  • Patent number: 10790312
    Abstract: A display panel and a display device are provided. The display panel includes a base substrate, the base substrate includes a display region and a non-display region, the display region includes a main display region and a peripheral display region, and the peripheral display region includes an irregular display region; the non-display region includes a first region and a second region, the first region is adjacent to the irregular display region, and the second region is adjacent to other regions of the peripheral display region than the irregular display region; the display region includes at least one signal line, the non-display region includes at least one functional circuit and at least one wire, and the at least one functional circuit is coupled to the at least one signal line via the at least one wire.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 29, 2020
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yun Qiao, Zhen Wang, Lele Cong, Zhengkui Wang, Jianjun Zhang, Han Zhang, Wenwen Qin, Fei Huang, Xiaozhou Zhan, Peng Liu, Jian Sun
  • Publication number: 20200242996
    Abstract: A display panel, a display device and a display control method thereof are provided in the present disclosure. The display panel includes: a time division multiplexing multiplexer (MUX) signal input circuit, which is connected with each of the plurality of signal lines, and configured to input data signals of each frame of display image to the plurality of signal lines, and for each frame of display image, input trigger signals corresponding to sub-pixel units of different colors to the plurality of signal lines in a time-sharing manner; among the plurality of signal lines, electrical signals on a plurality of adjacent first signal lines are arranged in sequence according to an order of positive, positive, negative and negative; among the plurality of signal lines, a first signal line has a spacing distance from adjacent signal lines less than a preset value.
    Type: Application
    Filed: December 13, 2019
    Publication date: July 30, 2020
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen WANG, Han ZHANG, Zhengkui WANG, Wei YAN, Yun QIAO, Wenwen QIN, Xiaozhou ZHAN, Jian SUN, Jian ZHANG, Deshuai WANG