Abstract: Certain embodiments of the present technology described herein relate to detecting atrial oversensing in a His intracardiac electrogram (His IEGM), characterizing atrial oversensing, determining when atrial oversensing is likely to occur, and or reducing the chance of atrial oversensing occurring. Some such embodiments characterize and/or avoid atrial oversensing within a His IEGM. Other embodiments of the present technology described herein relate to determining whether atrial capture occurs in response to His bundle pacing (HBP). Still other embodiments of the present technology described herein relate to determining whether AV node capture occurs in response to HBP.

Abstract: Certain embodiments of the present technology described herein relate to detecting atrial oversensing in a His intracardiac electrogram (His IEGM), characterizing atrial oversensing, determining when atrial oversensing is likely to occur, and or reducing the chance of atrial oversensing occurring. Some such embodiments characterize and/or avoid atrial oversensing within a His IEGM. Other embodiments of the present technology described herein relate to determining whether atrial capture occurs in response to His bundle pacing (HBP). Still other embodiments of the present technology described herein relate to determining whether AV node capture occurs in response to HBP.

Abstract: A system is provided that includes one or more processors, and a memory coupled to the one or more processors. The memory stores program instructions, and the program instructions are executable by the one or more processors. When executed, the one or more processors obtain cardiac activity (CA) signals for a series of beats, and identify whether a characteristic of interest (COI) from a first segment of the CA signals exceeds a COI limit. The one or more processors also analyze morphology of the CA signals for the series of beats responsive to the first segment of the CA signals exceeding the COI limit, and based on the analyze operation, identify a premature ventricular contraction (PVC) within the series of beats.

Abstract: Systems and methods for His bundle pacing and classifying response to pacing impulses include applying, using a pulse generator, an impulse through a stimulating electrode to induce a response from a patient heart. A response to the impulse is measured using at least one sensing electrode and time-domain based characteristics of the response are analyzed to determine whether His bundle capture has occurred and, if so, what type of capture has occurred.

Abstract: An array substrate, a display panel, a display device, and driving methods thereof are provided. The array substrate includes subpixels arranged in an array, and switches. The subpixels include subpixels of a first color, subpixels of a second color, subpixels of a third color, subpixels of a fourth color, in odd rows of subpixels, the subpixels of the first color, the subpixels of the second color, the subpixels of the third color, the subpixels of the fourth color are sequentially arranged; in even rows of subpixels, the subpixels of the third color, the subpixels of the fourth color, the subpixels of the first color, the subpixels of the second color are sequentially arranged; and the subpixels of the first color are white subpixels; the subpixels of the second color are blue subpixels; the subpixels of the third color are green subpixels; the subpixels of the fourth color are red subpixels.

Abstract: System and methods are provided herein and include a HIS electrode configured to be located proximate to a HIS bundle and to at least partially define a HIS sensing vector. They system includes memory to store program instructions and cardiac activity (CA) signals for a series of beats utilizing a candidate sensing configuration. The candidate sensing configuration is defined by i) the HIS sensing vector and ii) a sensing channel that utilizes sensing circuitry configured to operate based on one or more sensing settings to detect near field and far field activity. The system includes one or more processors that, when executing the program instructions, are configured to analyze the CA signals to obtain an atrial (A) feature of interest (FOI) and a ventricular (V) FOI for the corresponding beats within the series of beats and identify a V-A FOI relation between the A FOIs and the V FOIs across the series of beats.

Abstract: A system and method for managing atrial-ventricular (AV) delay adjustments are provided and includes electrodes configured to be located proximate to an atrial (A) site and at least one of a left bundle branch (LBB) site or a HIS site. An IMD has a header that includes a right atrial (RA) header port, a right ventricular (RV) header port and a left ventricular (LV) header port. The system includes memory configured to store program instructions and one or more processors that, when configured to execute the program instructions measure an AV interval corresponding to an interval between an atrial paced (Ap) event or an atrial sensed (As) event and a sensed ventricular (Vs) event.

Abstract: A touch display substrate and a display device are provided. The touch display substrate includes a plurality of sub-pixel units (10), data lines (20) and touch signal lines (30). For any two adjacent rows of sub-pixel units, the sub-pixel unit (10) in one row of sub-pixel units is staggered in a row direction with respect to the sub-pixel unit (10) in the other row of sub-pixel units adjacent to the one row of sub-pixel units by a distance of X sub-pixel units (10), and 0<X<1; these two sub-pixel units (10) have different colors. Data lines (20) and touch signal lines (30) are at gaps which extend in a column direction and are between the plurality of sub-pixel units (10). The touch signal lines (30) and the data lines (20) are in a same layer and the touch signal lines (30) are insulated from the data lines (20).

Abstract: A system and method are provided. The system includes a HIS electrode configured to be located proximate to a HIS bundle. A pulse generator is coupled to the HIS electrode and is configured to deliver HIS bundle pacing (HBP), a right atrial (RA) electrode is located in a right atrium, a sensing circuitry coupled to the RA electrode and defines an RA sensing channel that does not utilize the HIS electrode. The system includes a memory including program instructions. The system includes a processor is configured to collect cardiac activity (CA) signals over the RA sensing channel utilizing the RA electrode. The CA signals include a far field (FF) component associated with a ventricular event (VE). The processor analyzes the FF component to identify first and second FF component (FFC) characteristics of interest (COI) of the ventricular event and utilizes the first FFC COI to apply a first capture class (CC) discriminator to distinguish between first and second capture classes.

Abstract: A wiring structure includes a plurality of first connection lines disposed in a first wiring layer and extending respectively from first ones of the plurality of first electrical contacts to first ones of the plurality of second electrical contacts, the first connection lines not intersecting each other; and a plurality of second connection lines disposed in a second wiring layer and extending respectively from second ones of the plurality of first electrical contacts to second ones of the plurality of second electrical contacts, the second connection lines not intersecting each other. An orthographic projection of any one of the first connection lines onto a plane parallel to the first and second wiring layers does not intersect an orthographic projection of any one of the second connection lines onto the plane.

Abstract: A liquid crystal display panel and a display device. The liquid crystal display panel includes a display region and an opening region in the display region; the display region includes a plurality of sub-pixels, the display region includes a first edge and a second edge opposite to the first edge, the display region includes a first region between the opening region and the first edge and a second region between the opening region and the second edge, an orthographic projection of the opening region on the first edge respectively coincides with orthographic projections of the first region and the second region on the first edge, the plurality of sub-pixels comprise a main sub-pixel in the first region and a secondary sub-pixel in the second region, and an area of the main sub-pixel is smaller than an area of the secondary sub-pixel.

Abstract: A touch display substrate and a display device are provided. The touch display substrate includes a plurality of sub-pixel units (10), data lines (20) and touch signal lines (30). For any two adjacent rows of sub-pixel units, the sub-pixel unit (10) in one row of sub-pixel units is staggered in a row direction with respect to the sub-pixel unit (10) in the other row of sub-pixel units adjacent to the one row of sub-pixel units by a distance of X sub-pixel units (10), and 0<X<1; these two sub-pixel units (10) have different colors. Data lines (20) and touch signal lines (30) are at gaps which extend in a column direction and are between the plurality of sub-pixel units (10). The touch signal lines (30) and the data lines (20) are in a same layer and the touch signal lines (30) are insulated from the data lines (20).

Abstract: A liquid crystal display panel and a display device. The liquid crystal display panel includes a display region and an opening region in the display region; the display region includes a plurality of sub-pixels, the display region includes a first edge and a second edge opposite to the first edge, the display region includes a first region between the opening region and the first edge and a second region between the opening region and the second edge, an orthographic projection of the opening region on the first edge respectively coincides with orthographic projections of the first region and the second region on the first edge, the plurality of sub-pixels comprise a main sub-pixel in the first region and a secondary sub-pixel in the second region, and an area of the main sub-pixel is smaller than an area of the secondary sub-pixel.

Abstract: The present application provides a shift register unit, a shift register circuit, a driving method, and a display apparatus, and relates to the field of display technology. The method includes: in a reset phase in which a second node is at a first level, transmitting, by a control circuit, a second level signal to a first node and an output signal terminal under the control of a voltage at the second node; and in a normal operation phase, normally operating, by the shift register unit.

Abstract: An array substrate, a display panel, a display device, and driving methods thereof are provided. The array substrate includes subpixels arranged in an array, and switches. The subpixels include subpixels of a first color, subpixels of a second color, subpixels of a third color, subpixels of a fourth color, in odd rows of subpixels, the subpixels of the first color, the subpixels of the second color, the subpixels of the third color, the subpixels of the fourth color are sequentially arranged; in even rows of subpixels, the subpixels of the third color, the subpixels of the fourth color, the subpixels of the first color, the subpixels of the second color are sequentially arranged; and the subpixels of the first color are white subpixels; the subpixels of the second color are blue subpixels; the subpixels of the third color are green subpixels; the subpixels of the fourth color are red subpixels.

Abstract: An array substrate includes plural sub-pixels in plural rows and plural columns; plural data ports; Ndl data lines, each of the Ndl data lines connecting to a column of sub-pixels, the Ndl data lines being divided into plural groups, each group including N data lines; and a multiplexer including M control lines and plural switching units in one-to-one correspondence with the Ndl data lines, each control line being connected to and controlling Ndl M switching units. All of the N data lines in each group are connected to one data port through N switching units, respectively, the data lines in different groups are connected to different data ports, the N switching units corresponding to each group are controlled by N different control lines, respectively, and at least two of the N data lines in each group are provided with a data line another group therebetween.

Abstract: Disclosed are an array substrate, a liquid crystal display panel and a display apparatus. The array substrate comprises a plurality of pixel units, with each of which being provided with a plurality of sub-pixels (R, G, B) arranged in a first direction; a plurality of touch control electrodes, a region where each of the touch control electrodes is located overlapping with a region where the plurality of sub-pixels (R, G, B) are located; and a plurality of touch control signal lines arranged in gaps between the sub-pixels (R, G, B), wherein each of the touch control signal lines is connected to each of the touch control electrodes, there is no touch control floating signal line not connected to each of the touch control electrodes, and one column of pixel units is correspondingly provided with one touch control signal line.

Abstract: A touch array baseplate panel, including a substrate and a film layer structure. The film layer structure includes: a touch electrode layer, including a plurality of touch electrodes arranged in an array; a first electrically conductive layer, including a plurality of touch electrode lines and virtual touch electrode lines; a second electrically conductive layer, including connection lines. A touch electrode line is electrically connected to a corresponding touch electrode through a first via hole, and a virtual touch electrode line is electrically connected to a corresponding touch electrode through a second via hole, and a connection line electrically connects, through third via holes, a touch electrode line and a virtual touch electrode line electrically connected to a same touch electrode. This disclosure further provides a method for manufacturing the touch array baseplate panel and a touch panel including the touch array baseplate panel.

Abstract: A shift register unit, a method of driving a shift register unit, a gate driving circuit and a touch display device are disclosed. The shift register unit includes a first signal input terminal, a first voltage control terminal, a second signal input terminal, a second voltage control terminal, a signal output terminal, a first voltage terminal, and a second voltage terminal. The shift register unit further comprises a first input circuit, a second input circuit, an output circuit, an anti-leakage circuit, a first control circuit, and a second control circuit. The anti-leakage circuit is configured to bring a first node into conduction with a second node in response to an active potential of the second voltage terminal.

Abstract: A touch panel including a substrate, an insulating layer, touch electrode blocks, and electrode lines. The touch electrode blocks include an array of first type touch electrode blocks having a regular shape and a second type touch electrode block having an irregular shape. Ones of the first type touch electrode blocks are electrically connected to respective ones of the electrode lines by respective X first contact vias extending through the insulating layer, and the respective X first contact vias are arranged along a straight line in a column direction. The second type touch electrode block is electrically connected to a first corresponding one of the electrode lines by Y second contact vias extending through the insulating layer, and the Y second contact vias are arranged along at least one straight line in the column direction. X and Y are natural numbers, and 0.75×X?Y?1.25×X.