Abstract: A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.

Abstract: In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.

Abstract: A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.

Abstract: In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each pillar pattern, and the gate electrode is formed by etching the conductive pattern using the spacer as an etch barrier.

Abstract: A method for fabricating a magnetic tunnel junction device includes forming a first magnetic layer, a dielectric layer, a second magnetic layer and a capping layer, selectively etching the capping layer and the second magnetic layer to form a first pattern, forming a short prevention layer on a sidewall of the first pattern, and etching the dielectric layer and the first magnetic layer using the capping layer and the short prevention layer as an etch barrier to form a second pattern.

Abstract: The present invention relates to a cleaner composition comprising an alkalic agent, sodium polyacrylate as ion exchanger, a sterilizer and water, and a cleaning method using the same. More particularly, the present invention relates to a cleaner composition comprising 5 to 15 weight % of an alkalic agent, 5 to 20 weight % of sodium polyacrylate having a molecular weight 4,000 to 10,000 as ion exchanger, 0.5 to 30 weight % of a sterilizer, and water as remainder, and a cleaning method using the same. The cleaner composition of the present invention provides the effect of removing fats, proteins, minerals, etc. comparable to or better than that of the conventional cleaner, and can reduce cleaning time and cost because the cleaning process is simplified. Hence, it can be utilized to clean milking machines or other appliances.

Abstract: Disclosed is a method for fabricating a semiconductor device by using an amorphous carbon layer as a sacrificial hard mask. The method includes the steps of: forming an amorphous carbon layer on an etch target layer; forming a photoresist pattern on the amorphous carbon layer; etching the amorphous carbon layer by using the photoresist pattern to form a sacrificial hard mask; and etching the etch target layer by using the sacrificial hard mask to form a predetermined pattern.

Abstract: The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as an etch mask along with use of a plasma containing CHF3 gas to form a sacrificial hard mask; and etching the etch target layer by using at least the sacrificial hard mask as an etch mask, thereby obtaining a predetermined pattern.

Abstract: A method for fabricating a semiconductor device includes forming a conductive material layer for forming a gate over a substrate including a cell region and a peripheral region, forming hard mask patterns over the conductive material layer, forming a mask pattern over the resultant structure in the cell region, exposing the peripheral region, trimming the hard mask patterns in the peripheral region, removing the mask pattern, and etching the conductive material layer to form gate patterns using the hard mask patterns.

Abstract: A method for forming a metal line is provided. The method includes: forming a metal structure with a specific grain size on a substrate; forming a first hard mask layer on the metal structure; forming a second hard mask layer on the first hard mask layer; forming a photoresist pattern on the second hard mask layer; etching the second hard mask layer using the photoresist pattern as an etch barrier, thereby obtaining first hard masks; etching the first hard mask layer using the first hard masks as an etch barrier, thereby obtaining second hard masks; and etching the metal structure using the first hard masks as an etch barrier.

Abstract: The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as an etch mask along with use of a plasma containing CHF3 gas to form a sacrificial hard mask; and etching the etch target layer by using at least the sacrificial hard mask as an etch mask, thereby obtaining a predetermined pattern.

Abstract: Disclosed is a method for fabricating a semiconductor device by using an amorphous carbon layer as a sacrificial hard mask. The method includes the steps of: forming an amorphous carbon layer on an etch target layer; forming a photoresist pattern on the amorphous carbon layer; etching the amorphous carbon layer by using the photoresist pattern to form a sacrificial hard mask; and etching the etch target layer by using the sacrificial hard mask to form a predetermined pattern.

Abstract: The present invention relates to a method for forming a metal line in a semiconductor memory device having a word strapping structure. Especially, the metal line is formed by using a dual hard mask including a tungsten layer and a nitride layer as an etch mask. Also, the metal line includes at least more than one metal layer based on a material selected from titanium nitride and aluminum. Furthermore, for the formation of the dual hard mask, a photoresist pattern to which an ArF photolithography process and a KrF photolithography process are applicable is used. The method includes the steps of: forming a metal structure on a substrate; forming a dual hard mask on the metal structure; forming a photoresist pattern on the dual hard mask; patterning the dual hard mask by using the photoresist pattern as an etch mask; and patterning the metal structure by using the dual hard mask, thereby obtaining the metal line.

Abstract: The present invention relates to a method for fabricating a semiconductor device with a capacitor by performing a plasma blanket etch-back process without employing a supplemental layer for isolating lower electrodes. The method includes the steps of: forming an insulation layer with a plurality of openings on a substrate to form lower electrodes; forming a conductive layer on the insulation layer; and etching first portions of the conductive layer formed outside the openings in a faster rate than second portions of the conductive layer formed inside the openings, thereby isolating the lower electrodes from each other.

Abstract: The present invention relates to a method for forming a storage node contact plug of a semiconductor device. The method includes the steps of: forming a bit line structure including a bit line and a hard mask on a substrate; forming a spacer made of an oxide material at sidewalls of the bit line structure; forming a line type photoresist pattern arranged in a direction vertical to the bit line structure on a storage node contact area of the substrate; forming an inter-layer insulation layer on an entire surface of the resulting structure including the line type photoresist pattern such that the inter-layer insulation layer is filled into a space between the photoresist pattern; etching an upper portion of the inter-layer insulation layer to expose the photoresist pattern; and removing the exposed photoresist pattern to open the storage node contact area.

Abstract: A method for fabricating a semiconductor device includes sequentially forming a stopping layer, an intermetal dielectric, and a capping layer on an interlayer dielectric, selectively removing the capping layer, the intermetal dielectric, and the stopping layer to partially expose a surface of the interlayer dielectric to form a hole, selectively removing a side of the intermetal dielectric within the hole, depositing a metal film on an entire surface including the hole to form an air gap in a portion where the side of the intermetal dielectric is removed, and planarizing an entire surface of the metal film to expose a surface of the capping layer to form a plurality of metal lines.

Abstract: The present invention provides a method of dry etching capable of improving an etch selectivity of an etch target against a photoresist pattern during a process for etching a dielectric layer. The inventive method includes the steps of: forming an etch target layer on a substrate; forming a photoresist pattern on the etch target layer; and etching etch target layer by using the photoresist pattern as an etch mask and a mixed gas of C4F6 and CH2F2.

Abstract: The present invention relates to a method for removing polysilicon layers used as a hard mask from contact holes without damaging the semiconductor substrate during the etching process. The present invention according to the present invention comprises the steps of: forming a nitride layer on a contact region to be contacted with a conducting layer; forming an interlayer insulation layer on the nitride layer, wherein the interlayer insulation layer has a different etching rate from the nitride layer so that the nitride layer acts as an etching barrier layer for the interlayer insulation layer; forming a polysilicon pattern on the interlayer insulation layer; etching the interlayer insulation layer using the polysilicon pattern as an etching mask, whereby a first opening to expose a portion of the nitride layer is formed; and etching the exposed nitride layer, thereby forming a second opening to expose the contact region.

Abstract: A method for fabricating a semiconductor device includes sequentially forming a stopping layer, an intermetal dielectric, and a capping layer on an interlayer dielectric, selectively removing the capping layer, the intermetal dielectric, and the stopping layer to partially expose a surface of the interlayer dielectric to form a hole, selectively removing a side of the intermetal dielectric within the hole, depositing a metal film on an entire surface including the hole to form an air gap in a portion where the side of the intermetal dielectric is removed, and planarizing an entire surface of the metal film to expose a surface of the capping layer to form a plurality of metal lines.

Abstract: The present invention relates to a method for removing polysilicon layers used as a hard mask from contact holes without damaging the semiconductor substrate during the etching process. The present invention according to the present invention comprises the steps of: forming a nitride layer on a contact region to be contacted with a conducting layer; forming an interlayer insulation layer on the nitride layer, wherein the interlayer insulation layer has a different etching rate from the nitride layer so that the nitride layer acts as an etching barrier layer for the interlayer insulation layer; forming a polysilicon pattern on the interlayer insulation layer; etching the interlayer insulation layer using the polysilicon pattern as an etching mask, whereby a first opening to expose a portion of the nitride layer is formed; and etching the exposed nitride layer, thereby forming a second opening to expose the contact region.