Abstract: An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.

Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: A light source module includes a substrate, a first illumination element, a second illumination element and a third illumination element. The first illumination element includes a blue LED chip disposed on the substrate and a first wavelength converting layer that covers the blue LED chip, in which blue light emitted from the blue LED chip can be converted to light in the range of a first wavelength. The second illumination element includes a blue LED chip disposed on the substrate and a second wavelength converting layer that covers the blue LED chip, in which blue light emitted from the blue LED chip can be converted to light in the range of a second wavelength. The third illumination element includes a blue LED chip.

Abstract: An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a global line pair including a global bit line and a global source line; a plurality of cell matrices coupled between the global bit line and the global source line, each cell matrix including a plurality of local line pairs and a plurality of storage cells that are coupled to the plurality of local line pairs, wherein each storage cell is operable to store data and is coupled between local lines of a corresponding local line pair; and a plurality of isolation switch pairs that couple the plurality of cell matrices to the global bit line and the global source line of the global line pair, one isolation switch pair per cell matrix.

Abstract: A physiological detection device includes a main body, a sensor pair, a signal processor, and a calculation module. The sensor pair is disposed in the main body and adapted to detect a detected portion of a human body, so as to obtain a sensing signal. The signal processor is disposed in the main body and receives and processes the sensing signal, so as to output a digital physiological signal. The calculation module receives the digital physiological signal and calculates to obtain first information and second information of a plurality of feature points of the digital physiological signal. The calculation module calculates a ratio of the second information to the first information, so as to obtain a physiological state index. The digital physiological signal includes a plurality of pulse waves generated according to a time sequence.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a global line pair including a global bit line and a global source line; a plurality of cell matrices coupled between the global bit line and the global source line, each cell matrix including a plurality of local line pairs and a plurality of storage cells that are coupled to the plurality of local line pairs, wherein each storage cell is operable to store data and is coupled between local lines of a corresponding local line pair; and a plurality of isolation switch pairs that couple the plurality of cell matrices to the global bit line and the global source line of the global line pair, one isolation switch pair per cell matrix.

Abstract: An optical lens includes seven lenses. An first lens has a negative refractive power: an second lens, an third lens, an fifth lens, an sixth lens and an seventh lens have refractive powers respectively, and the fourth lens has a positive refractive power. One of the second lens and the third lens has a positive refractive power, and the other has a negative refractive power. One of the fifth lens and the sixth lens has a positive refractive power and the other has a negative refractive power. An object-side surface of the first lens has a refractive rate R1, an image-side surface of the first lens has a refractive rate R2, and |R2/R1|?0.01.

Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.

Abstract: A circulator apparatus comprises a housing, a processing module, and a display, a heater, and a motor are coupled to the processing module. The motor has a shaft connected to an impeller. The circulator apparatus further comprises a stand, and the stand has a base member, a supporting member, and a mounting member. Two ends of the supporting member are connected the base member and the mounting member respectively, the supporting member is configured to lift the housing, so the bottom side of the housing is located away from the base member by a predetermined distance.

Abstract: A wireless temperature maintenance container has an accommodating space accommodating a transmitter circuit and a receiver circuit. The transmitter circuit comprises a first power processing circuit and a transmitter coil. The first power processing circuit receives a utility power and outputs a first direct current. The transmitter coil receives the first direct current and generates a magnetic field. The receiver circuit comprises a receiver coil, a second power processing circuit and a temperature controller. The magnetic field passes the receiver coil and an alternating current is generated. The second power processing circuit receives the alternating current and outputs a second direct current. The temperature controller receives the second direct current to control the temperature of the container. The transmitter circuit is on the first circuit board, and the receiver circuit is on the second circuit board. Distance between the first circuit board and the second board is 2 mm˜4 mm.

Abstract: A by-pass shunt for use with a bodily fluid pump. The by-pass shunt includes an inflow conduit, an outflow conduit, and an intermediate conduit fluidically coupling the inflow and outflow conduits. A flow restrictor is operably coupled to a portion of the intermediate conduit and is configured to reduce a fluid flow from the outflow conduit, through the intermediate conduit, and into the inflow conduit.

Abstract: An electronic device including a semiconductor memory is provided to include a mat region comprising a plurality of memory cells, each including a second transistor; a first switching region located at a side of the mat region and including first transistors; and a second switching region located at the other side of the mat region and including third transistors, wherein the second transistors comprise: a plurality of second active regions; and a plurality of second gate structures extending in the first direction to cross the second active regions, wherein each second active regions is divided into a first side portion, a middle portion and a second side portion that are arranged alternately and repeatedly in the first direction, wherein the first transistors and the third transistors include their active regions and gate structures which are arranged in the same manner as those of the second transistors.

Abstract: Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate on both sides of the buried gate, isolation layers each formed between a sidewall of the open part and a sidewall of the buried gate, source/drain regions formed in the substrate under the respective open parts, and contact plugs buried in the respective open parts.

Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.

Abstract: An optical lens includes seven lenses. An first lens has a negative refractive power: an second lens, an third lens, an fifth lens, an sixth lens and an seventh lens have refractive powers respectively, and the fourth lens has a positive refractive power. One of the second lens and the third lens has a positive refractive power, and the other has a negative refractive power. One of the fifth lens and the sixth lens has a positive refractive power and the other has a negative refractive power. An object-side surface of the first lens has a refractive rate R1, an image-side surface of the first lens has a refractive rate R2, and |R2/R1|?0.

Abstract: This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. In accordance with the electronic device of this patent document, an area can be reduced, device characteristics can be improved due to a reduction in the resistance of the switching transistor, the process can be simplified, and a cost can be reduced.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.