Abstract: A nonvolatile memory apparatus includes: a memory cell coupled to a bit line and a source line; a word line configured to select the memory cell; and a local switch block configured to apply a write voltage, a read voltage, and a source line voltage to the bit line and the source line in response to a local switch select signal. In a write or read operation of the nonvolatile memory apparatus, the word line has a first voltage level, and the local switch select signal has a second voltage level higher than the first voltage level.

Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar. array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.

Abstract: A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.

Abstract: Provided is an electronic device including a semiconductor memory unit. The semiconductor memory unit may include: a storage cell comprising a variable resistance element; a first selecting element coupled to one end of the storage cell and having a threshold voltage set to a first voltage; and a second selecting element coupled to the other end of the storage cell and having a threshold voltage set to a second voltage higher than the first voltage.

Abstract: A light emitting diode (LED) device includes a transparent substrate, a first reflection layer, a LED chip, a positive electrode, a negative electrode and a wavelength-converting layer. The LED chip is disposed on a surface of the transparent substrate, and the first reflection layer is disposed between the LED chip and the transparent substrate. The positive electrode and the negative electrode are disposed on an end portion of the transparent substrate and are electrically connected with the LED chip. The wavelength-converting layer covers the first reflection layer and the LED chip.

Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.

Abstract: A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

Abstract: This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. In accordance with the electronic device of this patent document, an area can be reduced, device characteristics can be improved due to a reduction in the resistance of the switching transistor, the process can be simplified, and a cost can be reduced.

Abstract: Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate on both sides of the buried gate, isolation layers each formed between a sidewall of the open part and a sidewall of the buried gate, source/drain regions formed in the substrate under the respective open parts, and contact plugs buried in the respective open parts.

Abstract: Provided is an electronic device including a semiconductor memory which includes a cell array region having a first variable resistance element and a peripheral circuit region having a decoupling capacitor, the decoupling capacitor including a bottom electrode, a dielectric layer pattern, and a top electrode. The cell array region may include: a first gate; a first contact over the first gate; a second contact over an active region at one side of the first gate; and the first variable resistance element over the second contact, and the peripheral circuit region may include: a second gate formed of the same material at the same level as the first gate; the bottom electrode disposed over the second gate and formed at the same level as the first contact; and the dielectric layer pattern and the top electrode disposed over the bottom electrode.

Abstract: A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

Abstract: A mobile electronic device is provided, including a first housing, a second housing and a circuit board assembly. The first housing is connected to the second housing to form a receiving space with the circuit board assembly disposed therein. The circuit board assembly includes a first circuit board having a plurality of light emitting diodes, a second circuit board, and a frame disposed between the first circuit board and the second circuit board.

Abstract: A variable resistance memory device includes vertical electrodes vertically projecting from a substrate, first horizontal electrodes stacked along the vertical electrodes, second horizontal electrodes stacked along the vertical electrodes, and a variable resistance layer interposed between the vertical electrodes and the first and second horizontal electrodes, wherein the first and second horizontal electrodes are arranged in directions crossing with each other.

Abstract: A linear motion guide device includes a slider slidably attached onto a guide rail, two dust caps oppositely attached to end portions of the slider respectively and each having a channel formed between two legs for slidably engaging with the guide rail, and each having a lip portion directed toward the guide rail for wiping the engaging surface of the guide rail, and the lip portions of the legs of the dust caps each include an inner flange directed toward the slider and each include a number of notches and a number of projections formed in the inner flange of each of the legs and offset from each other for wiping the lubricating fluid into the notches of the legs respectively.

Abstract: This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. In accordance with the electronic device of this patent document, an area can be reduced, device characteristics can be improved due to a reduction in the resistance of the switching transistor, the process can be simplified, and a cost can be reduced.

Abstract: Provided is an electronic device including a semiconductor memory unit. The semiconductor memory unit may include: a storage cell comprising a variable resistance element; a first selecting element coupled to one end of the storage cell and having a threshold voltage set to a first voltage; and a second selecting element coupled to the other end of the storage cell and having a threshold voltage set to a second voltage higher than the first voltage.

Abstract: Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate on both sides of the buried gate, isolation layers each formed between a sidewall of the open part and a sidewall of the buried gate, source/drain regions formed in the substrate under the respective open parts, and contact plugs buried in the respective open parts.

Abstract: An application installation method of a wearable device is provided. The application installation method of a wearable device includes the steps of: receiving an installation application package from a smart device via a wireless transmission, wherein the installation application package is used for installing an application; parsing the installation application package to obtain an application installation file corresponding to the application; and using the application installation file to install the application on the wearable device.