Patents by Inventor Yunfei Deng

Yunfei Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190267598
    Abstract: A heat-resistant multi-layer composite lithium-ion battery separator, and coating device and manufacturing method for same. The battery separator comprises a base membrane (12) having two end faces provided with a coating paste, and the end faces of the base membrane (12) are both adhered with a composite layer via the coating paste. The composite layer comprises one, two, or multiple composite films (13). The composite films (13) are adhered and fixed via the coating paste. The coating device is employed during the manufacturing, and comprises a base membrane uncoiling reel (1), a coating roller (2), a composite film uncoiling mechanism, a heating and drying mechanism, and a coiling reel (6). The coating roller (2) is arranged in a one-to-one correspondence to the composite film uncoiling mechanism, and two sets of the coating roller and the composite film uncoiling mechanism are provided on two sides of the base membrane (12).
    Type: Application
    Filed: September 13, 2017
    Publication date: August 29, 2019
    Inventors: Feng Xu, Haichao Yuan, Yunfei Deng, Wenxian Ma
  • Publication number: 20190232366
    Abstract: The invention belongs to the fields of amorphous alloy composites, additive manufacturing technology and hot isostatic pressing sintering forming, and in particular relates to a preparation method of tungsten particle reinforced amorphous matrix composites, comprising the following steps: (1) making tungsten powder and amorphous alloy powder into a preform by the micro-jetting and bonding 3D printing technology, specifically comprising: in the preforming process by micro-jetting and bonding, through a double-drum type powder feeding device, spraying tungsten powder and amorphous alloy powder into a layer of uniformly mixed powder layer by double nozzles, then bonding the powder layer into a bonding layer by the binder, and repeating the operations of spraying the powders and binder, so that a preform with uniform particle phase distribution is finally prepared; (2) placing the preform in a capsule, and performing heating and vacuumizing on the capsule in a heating furnace; and (3) placing the capsule in the h
    Type: Application
    Filed: March 30, 2018
    Publication date: August 1, 2019
    Inventors: Pan GONG, Xinyun WANG, Yunfei MA, Lei DENG, Junsong JIN
  • Publication number: 20190224753
    Abstract: The present invention discloses a cold additive and hot forging combined forming method of amorphous alloy parts.
    Type: Application
    Filed: April 24, 2018
    Publication date: July 25, 2019
    Inventors: Xinyun WANG, Pan GONG, Yunfei MA, Lei DENG, Junsong JIN
  • Patent number: 9678435
    Abstract: Aspects of the disclosed techniques relate to techniques for resist simulation in lithography. Local minimal light intensity values are determined for a plurality of sample points in boundary regions of an aerial image of a feature to be printed on a resist coating, wherein each of the local minimal light intensity values represents a minimum light intensity value for an area surrounding one of the plurality of sample points. Based on the local minimal light intensity values, horizontal development bias values for the plurality of sample points are then determined. Finally, resist contour data of the feature are determined based at least on the horizontal development bias values.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: June 13, 2017
    Assignee: Mentor Graphics, A Siemens Business
    Inventors: Yunfei Deng, Yuri Granik, Dmitry Medvedev, Yuan He, Konstantinos Adam
  • Publication number: 20160140278
    Abstract: Aspects of the disclosed techniques relate to techniques for resist simulation in lithography. Local light power values are determined for a plurality of sample points in boundary regions of an aerial image of a feature to be printed on a resist coating, wherein each of the local light power values represents a light power value for an area surrounding one of the plurality of sample points. Based on the local light power values, a vertical shrinkage function is constructed. Resist contour data of the feature are then computed based at least on resist shrinkage effects modeled using the local light power values and the vertical shrinkage function.
    Type: Application
    Filed: January 25, 2016
    Publication date: May 19, 2016
    Inventors: Yunfei Deng, Yuri Granik, Dmitry Medvedev, Konstantinos Adam
  • Publication number: 20150311122
    Abstract: Methods for forming abutting FinFET cells with a single dummy gate and continuous fins, and the resulting devices, are disclosed. Embodiments may include forming one or more continuous fins on a substrate, forming gates perpendicular to and over the one or more continuous fins to form a first FinFET cell and a second FinFET cell, and forming source and drain contact lines parallel to and between the gates, wherein a source contact line of the first FinFET cell is adjacent to a drain contact line of the second FinFET cell, and the source contact line and the drain contact line are on opposite sides of a gate.
    Type: Application
    Filed: April 28, 2014
    Publication date: October 29, 2015
    Applicant: Globalfoundries Inc.
    Inventors: Mahbub RASHED, Yunfei DENG, Juhan KIM, Jongwook KYE, Suresh VENKATESAN, Subramani KENGERI
  • Patent number: 9142513
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook K E, Roderick Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
  • Publication number: 20150187702
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Application
    Filed: March 12, 2015
    Publication date: July 2, 2015
    Inventors: Mahbub RASHED, Yuansheng MA, Irene LIN, Jason STEPHENS, Yunfei DENG, Lei YUAN, Jongwook KYE, Rod AUGUR, Shibly AHMED, Subramani KENGERI, Suresh VENKATESAN
  • Publication number: 20150108583
    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Mahbub Rashed, Johan Kim, Yunfei Deng, Suresh Venkatesan
  • Patent number: 9006100
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8975712
    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
  • Patent number: 8962483
    Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Youngtag Woo, Dinesh Somasekhar, Juhan Kim, Yunfei Deng, Jongwook Kye
  • Patent number: 8966423
    Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye
  • Patent number: 8916441
    Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Jongwook Kye, Suresh Venkatesan
  • Publication number: 20140339647
    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 20, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
  • Publication number: 20140339610
    Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 20, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Jongwook Kye, Suresh Venkatesan
  • Patent number: 8881083
    Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yunfei Deng, Lei Yuan, Hidekazu Yoshida, Juhan Kim, Mahbub Rashed, Jongwook Kye
  • Publication number: 20140273474
    Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Youngtag WOO, Dinesh Somasekhar, Juhan Kim, Yunfei Deng, Jongwook Kye
  • Publication number: 20140258960
    Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye
  • Patent number: 8689154
    Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: April 1, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Mahbub Rashed, David Doman, Dinesh Somasekhar, Yan Wang, Yunfei Deng, Navneet Jain, Jongwook Kye, Ali Keshavarzi, Subramani Kengeri, Suresh Venkatesan