Abstract: Disclosed are a pile-bottom grouting cavity and a method for using same, and a cast-in-place pile body and a method for constructing same. The pile-bottom grouting cavity comprises: a grouting capsule, having an expansion state in which the grouting capsule is filled with grout to bear a pile body, and a contracted state in which the grouting capsule is hollow; a grouting pipe in communication with an inner cavity of the grouting capsule to grout the grouting capsule; and a fixing plate, with the grouting capsule being arranged on the fixing plate, and the fixing plate being provided with a through hole that is in communication with the bottom of an accommodation hole, such that slurry and/or sediment in the accommodation hole pass through the fixing plate. The aim thereof is to solve the problems in the prior art of hole wall collapse and excessive sediment that seriously affect the quality of construction in a grouting pile with a grouting capsule during the construction of a cast-in-place bored pile.

Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.

Abstract: A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric material and the electrode. Related semiconductor devices comprising at least one transistors, related electronic systems, and related methods are also disclosed.

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.

Abstract: An example apparatus includes a first transistor and a second transistor, each having asymmetric source/drain regions. A source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor at a junction. A depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor.

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.

Abstract: Redox catalysts having surface medication, methods of making redox catalysts with surface modification, and uses of the surface modified redox catalysts are provided. In some aspects, the redox catalysts include a core oxygen carrier region such as CaMnO3, BaMnO3-?, SrMnO3-?, Mn2SiO4, Mn2MgO4-?, La0.8Sr0.2O3-?, La0.8Sr0.2FeO3-?, Ca9Ti0.1Mn0.9O3-?, Pr6O11-?, manganese ore, or a combination thereof; and an outer shell having an average thickness of about 1-100 monolayers surrounding the outer surface of the core region. The outer shell can include, for example a salt selected such as Li2WO4, Na2WO4, K2WO4, SrWO4, Li2MoO4, Na2MoO4, K2MoO4, CsMoO4, Li2CO3, Na2CO3, K2CO3, or a combination thereof.

Abstract: An example apparatus includes a first transistor and a second transistor, each having asymmetric source/drain regions. A source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor at a junction. A depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor.

Abstract: In one aspect, the disclosure relates to a process for dehydrogenating a first dehydrogenation reactant into its unsaturated counterparts. The disclosed process comprises introducing a dehydrogenation reactant to a metal oxide catalyst having dehydrogenation activity, and dehydrogenating the dehydrogenation reactant to provide its unsaturated counterpart and hydrogen; selectively combusting the hydrogen released during dehydrogenation using a lattice oxygen from the metal oxide catalyst, resulting in a reduced metal oxide catalyst and steam; re-oxidizing the reduced metal oxide catalyst by introducing a gaseous oxidant to the reduced metal oxide catalyst; and optionally re-using the re-oxidized metal oxide catalyst for catalytic conversion and combustion. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.

Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.