Abstract: A computer readable recording media comprising at least one program code recorded thereon, a touch control method is performed when the program code is read and executed. The touch control method comprises the following steps: (a) detecting location data for an object relative to a detecting surface to generate at least one displacement data; (b) storing the displacement data to a storage apparatus and outputting the stored displacement data to a target apparatus from the storage apparatus after storing the displacement data for a predetermined time period, when the object touches the detecting surface; and (c) cleaning the stored displacement data when the object leaves the detecting surface.

Abstract: An optical navigation apparatus and an optical navigation method are provided. The optical navigation apparatus includes a light source unit, an image sensing unit, and a processing unit, wherein the processing unit is electrically connected to the light source unit and the image sensing unit. The light source unit generates a beam of light. The image sensing unit captures a plurality of images within a time interval. The processing unit determines that the beam of light is projected onto a touch object according to the images, calculates a piece of displacement information related to the touch object according to the images, generates a comparison result by comparing the piece of displacement information with a threshold, and sets a displacement resolution of the optical navigation apparatus according to the comparison result.

Abstract: An inductor formed on a semiconductor substrate includes a semiconductor substrate, an inductor structure formed on the semiconductor substrate, and a plurality of slice structures formed in the semiconductor substrate. An extending direction of the slice structures is perpendicular to a surface of the semiconductor substrate. The slice structures are overlapped by the inductor.

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract: A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer.

Abstract: A transmission interface has a quick burst motion readout mechanism and is configured to be used between a master device and a slave device. The transmission interface includes a trigger channel configured to allow the master device to transmit a trigger signal to the slave device before transmission of data, and includes a data transmission channel provided to the slave device to transmit readable data to the master device after the slave device receives the trigger signal. The master and slave devices are adapted to a predetermined data transmission protocol by which the readable data can be directly transmitted and not accompanied by address data related to the readable data.

Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connection unit providing a signal to the RF circuit.

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract: A semiconductor process is described in this application. The process includes the following steps: providing a semiconductor substrate; measuring a warpage level of the semiconductor substrate; and holding the semiconductor substrate by providing at least one vacuum suction according to the warpage level, so that the semiconductor substrate is subjected to a plurality of varied suction intensities. The semiconductor substrate is held on a chuck having a plurality of holes grouped into a plurality of groups, and the sizes of the holes within different groups are different, wherein the sizes of the holes increase from a center toward an edge of the chuck, and the holes are arranged in a spiral.

Abstract: A semiconductor process is described in this application. The process includes the following steps: providing a semiconductor substrate; measuring a warpage level of the semiconductor substrate; and holding the semiconductor substrate by providing at least one vacuum suction according to the warpage level, so that the semiconductor substrate is subjected to a plurality of varied suction intensities. The semiconductor substrate is held on a chuck having a plurality of holes grouped into a plurality of groups, and the sizes of the holes within different groups are different, wherein the sizes of the holes increase from a center toward an edge of the chuck, and the holes are arranged in a spiral.

Abstract: A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

Abstract: A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist.

Abstract: A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.

Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Abstract: An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof.

Abstract: A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.

Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit.

Abstract: A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.

Abstract: An optical navigation device includes a first optical mechanism, a second optical mechanism, an image sensor, and a controller. The first optical mechanism is arranged for projecting light on a surface to generate a first projection result while the second optical mechanism is arranged for projecting light on the surface to generate a second projection result. The image sensor is arranged for sensing at least one of the first projection result and the second projection result within a sensing range to generate at least one first image sensing result. The controller is coupled to the first optical mechanism, the second optical mechanism and the image sensor, and is arranged for controlling the first optical mechanism and the second optical mechanism according to the first image sensing result. The optical navigation device accordingly performs movement detection.

Abstract: A semiconductor structure comprising a substrate, a dielectric layer, a conductor post, a first conductive layer structure and a second conductive layer structure is provided. The substrate comprises an opening structure. The dielectric layer is disposed on a sidewall of the opening structure. The conductor structure is disposed in the opening structure and covers the dielectric layer. The first and second conductive layer structures are electrically connected to the conductor post. A voltage difference is existed between the first and second conductive layer structures, such that a current is passing through the first conductive layer structure, the opening structure and second conductive layer structure. A resistance values is related to the voltage difference and the current. A dimension of the opening structure is 10 times greater than a dimension of the first and second conductive layer structures.