Patents by Inventor Yung-Chang Lin

Yung-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CHUCK AND SEMICONDUCTOR PROCESS USING THE SAME
    Publication number: 20140065553
    Abstract: An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chung-Sung JANG, Ming-Tse LIN, Yung-Chang LIN
  • Method of manufacturing flash memory cell
    Patent number: 8664062
    Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Memory Company
    Inventors: Yung-Chang Lin, Nan-Ray Wu, Le-Tien Jung
  • SEMICONDUCTOR DEVICE
    Publication number: 20130334669
    Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: Chien-Li Kuo, Yung-Chang Lin
  • SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    Publication number: 20130334699
    Abstract: A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: Chien-Li Kuo, Yung-Chang Lin
  • CHEMICAL VAPOR DEPOSITION OF GRAPHENE ON DIELECTRICS
    Publication number: 20130243969
    Abstract: A method for synthesizing graphene films is disclosed. Monolayer or multilayer graphene can be directly grown on the dielectric materials. The method includes the following steps: disposing dielectric materials and metals in a reactor, introducing reaction gases into the reactor and decomposing the reaction gases by heating, thus directly depositing graphene films on the surfaces of the dielectrics. High crystalline quality and low-defect graphene films can be synthesized directly on dielectric materials, without the process of wet etching and transfer. The method opens up a more direct route to apply graphene on electronics, optoelectronics, and bio-medical devices.
    Type: Application
    Filed: August 23, 2012
    Publication date: September 19, 2013
    Inventors: Po-Yuan TENG, Yung-Chang Lin, Po-Wen Chiu
  • COMPUTER READABLE MEDIA CAN PERFORM INTERFERENCE IMAGE DETERMINING METHOD AND INTERFERENCE IMAGE DETERMINING APPARATUS
    Publication number: 20130236051
    Abstract: A computer readable media having at least one program code recorded thereon. An interference image determining method can be performed when the program code is read and executed. The interference image determining method comprises: (a) controlling a light source to illuminate an object on a detecting surface to generate an image; (b) controlling a sensor to catch a current frame of the image; (c) utilizing an image characteristic included in the current frame to determine a interference image part of the current frame; and (d) updating a defined interference image according to the determined interference image part.
    Type: Application
    Filed: July 30, 2012
    Publication date: September 12, 2013
    Inventors: Hsin-Chia Chen, Yen-Min Chang, Yu-Hao Huang, Wen-Han Yao, Ching-Lin Chung, Yung-Chang Lin, Tsung-Fa Wang, Ming-Tsan Kao
  • Capacitor structure and method of forming the same
    Patent number: 8525296
    Abstract: The present invention provides a capacitor structure, comprising a substrate, a TSV, a dielectric layer and a doped region. The substrate includes a first surface and a second surface, which are disposed oppositely to each other. The TSV penetrates through the first surface and the second surface. The dielectric layer is disposed in the substrate and encompasses the TSV. The doped region is disposed between the dielectric layer and the substrate. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 3, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yung-Chang Lin, Chien-Li Kuo
  • Through Silicon Via and Method of Manufacturing the Same
    Publication number: 20130140688
    Abstract: The present invention discloses a through silicon via and method of manufacturing the same comprising the steps of providing a substrate, forming a plurality of through silicon via (TSV) holes in said substrate, forming a seed layer on the surface of said substrate and said a plurality of TSV holes, forming a patterned mask on said substrate, wherein said patterned mask comprises a plurality of first openings corresponding to said TSV holes and a plurality of second openings adjacent to or surrounding said a plurality of first openings, forming a material layer on said substrate, wherein said material layer is filled into said TSV holes and said first openings to form a plurality of through silicon vias, and said material layer is filled into said second openings to form a plurality of dummy bumps.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Chun-Hung Chen, Ming-Tse Lin, Yung-Chang Lin
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20130140708
    Abstract: A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Yung-Chang Lin, Chien-Li Kuo, Ming-Tse Lin, Sun-Chieh Chien
  • Chip stacking structure
    Patent number: 8441134
    Abstract: A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: May 14, 2013
    Assignee: United Microelectronics Corporation
    Inventors: Chien-Li Kuo, Yung-Chang Lin, Ming-Tse Lin
  • METHOD FOR TREATING OSTEOSARCOMA BY BORON NEUTRON CAPTURE THERAPY USING BORIC ACID AS A BORON DRUG
    Publication number: 20130102829
    Abstract: The present invention provides a treatment of osteosarcoma by boron neutron capture therapy using boric acid as a single boron drug.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: National Tsing Hua University
    Inventors: Fong-In CHOU, Chen-Fang SHU, Jinn-Jer PEIR, Hong-Ming LIU, Jiunn-Wang LIAO, Yung-Chang LIN
  • Trench-capacitor DRAM device and manufacture method thereof
    Patent number: 8415732
    Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: April 9, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Nan Su, Yung-Chang Lin, Jun-Chi Huang
  • Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse
    Patent number: 8399318
    Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: March 19, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
  • CHIP STACKING STRUCTURE
    Publication number: 20130062780
    Abstract: A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: United Microelectronics Corporation
    Inventors: Chien-Li KUO, Yung-Chang Lin, Ming-Tse Lin
  • Method of manufacturing a capacitor deep trench and of etching a deep trench opening
    Patent number: 8377829
    Abstract: A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: February 19, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Ta-Chuan Yeh, Ni-Min Chung, Kao-Su Huang, Yung-Chang Lin, Ruey-Chyr Lee, Chien-Kuo Wang
  • NETWORK DEVICE RELATING TO DIGITAL SUBSCRIBER LINE
    Publication number: 20120287976
    Abstract: A network device relating to a digital subscriber line (DSL) such as an asymmetrical DSL (ADSL) or a very high bit rate DSL (VDSL) is provided. In the present invention, the capacitors equipped into the network device are separated and grouped into two independent groups. When the network device runs out of power, the energy of one of the two independent groups is provided for generating the dying gasp signal, and the energy of the other of the two independent groups is provided for amplifying and transmitting the dying gasp signal to a Central Office (CO). Accordingly, the CO can be accurately known whether the network device runs out of power or not, and the respective capacitances of the two independent groups can be significantly reduced so as to reduce the cost of the network device.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 15, 2012
    Applicant: GEMTEK TECHNOLOGY CO., LTD.
    Inventors: Yu-Sung Cho, Yung-Chang Lin
  • Method and apparatus for buried word line formation
    Patent number: 8283715
    Abstract: An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and, a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line; wherein an etching rate of the separating layer approaches that of the substrate.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: October 9, 2012
    Assignee: Rexchip Electronics Corporation
    Inventors: Yung-Chang Lin, Sheng-Chang Liang
  • METHOD OF FORMING AN ELECTRICAL FUSE AND A METAL GATE TRANSISTOR AND THE RELATED ELECTRICAL FUSE
    Publication number: 20120228718
    Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
    Type: Application
    Filed: May 22, 2012
    Publication date: September 13, 2012
    Inventors: Yung-Chang LIN, Kuei-Sheng Wu, Chang-Chien Wong
  • METHOD OF FORMING AN ELECTRICAL FUSE AND A METAL GATE TRANSISTOR AND THE RELATED ELECTRICAL FUSE
    Publication number: 20120225524
    Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
    Type: Application
    Filed: May 10, 2012
    Publication date: September 6, 2012
    Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
  • Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse
    Patent number: 8227890
    Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: July 24, 2012
    Assignee: United Microelectronics Corporation
    Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong