Abstract: A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

Abstract: The method of forming a polycide gate includes forming a pad oxide layer on a substrate. A first conductive layer is formed on the pad oxide layer. Subsequently, a first ion implantation into the first conductive layer is next performed to form deep implantation region of polysilicon. Successively, a second ion implantation into the first conductive layer is performed to form shallow implantation region of polysilicon, wherein the second ion type is the same as the first ion type. A second conductive layer formed on the first conductive layer. A further patterned photoresist layer is formed on the second conductive layer. Next, a dry etching process one time by way of using the patterned photoresist layer as an etching mask is performed to etch through in turn the second conductive layer, the first conductive layer and the pad oxide layer until forming a gate with double polysilicon implantation, thereby forming a polycide gate. Finally, the photoresist layer is then removed.

Abstract: A memory structure and the method for fabricating the same are disclosed in this present invention. A first gate structure and a second gate structure are provided onto a substrate. After an implanting process, the first gate structure will become the periphery device of an embedded memory structure, and the second gate structure will become the memory device of the embedded memory structure. A first spacer and a second spacer are fabricated on the sidewalls of the first gate structure and the second gate structure. After the formation of the contacts between the second gate structures, the second spacer on the sidewall of the second gate structure will be removed. Therefore, there is the dual spacer, including the first spacer and the second spacer, on the sidewall of the first gate structure. In the other hand, the single spacer, only the first spacer included, is left on the sidewall of the second gate structure.

Abstract: A memory structure and the method for fabricating the same are disclosed in this present invention. A first gate structure and a second gate structure are provided onto a substrate. After an implanting process, the first gate structure will become the periphery device of an embedded memory structure, and the second gate structure will become the memory device of the embedded memory structure. A first spacer and a second spacer are fabricated on the sidewalls of the first gate structure and the second gate structure. After the formation of the contacts between the second gate structures, the second spacer on the sidewall of the second gate structure will be removed. Therefore, there is the dual spacer, including the first spacer and the second spacer, on the sidewall of the first gate structure. In the other hand, the single spacer, only the first spacer included, is left on the sidewall of the second gate structure.

Abstract: A memory structure and the method for fabricating the same are disclosed in this present invention. A first gate structure and a second gate structure are provided onto a substrate. After an implanting process, the first gate structure will become the periphery device of an embedded memory structure, and the second gate structure will become the memory device of the embedded memory structure. A first spacer and a second spacer are fabricated on the sidewalls of the first gate structure and the second gate structure. After the formation of the contacts between the second gate structures, the second spacer on the sidewall of the second gate structure will be removed. Therefore, there is the dual spacer, including the first spacer and the second spacer, on the sidewall of the first gate structure. In the other hand, the single spacer, only the first spacer included, is left on the sidewall of the second gate structure.

Abstract: A memory structure and the method for fabricating the same are disclosed in this present invention. A first gate structure and a second gate structure are provided onto a substrate. After an implanting process, the first gate structure will become the periphery device of an embedded memory structure, and the second gate structure will become the memory device of the embedded memory structure. A first spacer and a second spacer are fabricated on the sidewalls of the first gate structure and the second gate structure. After the formation of the contacts between the second gate structures, the second spacer on the sidewall of the second gate structure will be removed. Therefore, there is the dual spacer, including the first spacer and the second spacer, on the sidewall of the first gate structure. In the other hand, the single spacer, only the first spacer included, is left on the sidewall of the second gate structure.

Abstract: A liquid decoration container comprises an exhibition part, and a fitting part. The exhibition part is formed by way of blowing a hollow blank to constitute a hollow casing with a desirable shape and the hollow casing extends downward a cylindrical casing with an outer thread section. The fitting part is a base with an upper opening corresponding to the cylindrical casing and the upper opening provides an inner thread section. A ring plate is arranged to extend inward from an inner wall under the upper opening in the fitting part. The liquid is filled in the exhibition part and a doll is selectively fixed to or arranged on the ring plate. The cylindrical casing can engage with the upper opening by way of the outer thread section fastening to the inner thread section and a tight sealing can be performed as soon as a lower rim of the cylindrical casing touches the ring plate.

Abstract: A liquid decoration container comprises an exhibition part, and a fitting part. The exhibition part is formed by way of blowing a hollow blank to constitute a hollow casing with a desirable shape and the hollow casing extends downward a cylindrical casing with an outer thread section. The fitting part is a base with an upper opening corresponding to the cylindrical casing and the upper opening provides an inner thread section. A ring plate is arranged to extend inward from an inner wall under the upper opening in the fitting part. The liquid is filled in the exhibition part and a doll is selectively fixed to or arranged on the ring plate. The cylindrical casing can engage with the upper opening by way of the outer thread section fastening to the inner thread section and a tight sealing can be performed as soon as a lower rim of the cylindrical casing touches the ring plate.

Abstract: An ornamental device with thermal cycle of flame includes a heating section, and an exhibition section. The heating section has a base frame with an open top, the base frame providing a combustion room with an air aperture, the combustion room holding a combustible at a proper distance between the combustible and the open top. The exhibition section is an enclosed exhibiting container astride the base frame, containing a fluid medium of proper level to form an air chamber, and one or more exhibits being provided in the fluid medium. Once the combustible is lit, the flame heats up the fluid medium in the exhibiting container to a temperature of circulation. The fluid medium may generate a thermal cycle and circulate in the exhibiting container such that the exhibits may move with the circulating fluid medium and generate an effect of dynamic exhibition of tumbling upward and downward or floating and submerging alternately.

Abstract: A self-align offset gate structure and its method of manufacture. The method includes forming a damascene mask over a substrate and then forming gate openings over the damascene mask. Offset spacers are formed on the sidewalls of the gate openings and then sequentially forming a gate oxide layer and a conductive layer inside the gate opening. Chemical-mechanical polishing method is used to remove the conductive layer above the damascene mask surface. An ion implant is carried out implanting n-type ions or p-type ions into the conductive gate to form n-type or p-type gate respectively. The damascene mask is removed and then a lightly doped ion implant is conducted to form lightly doped source/drain regions. Finally, spacers are formed on the sidewalls of the gates and the offset spacers and then a heavily doped ion implant is carried out to form the heavily doped source/drain regions.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method can reduce thermal budget in node contact application. It includes mainly the following processes. A substrate is first provide, then a dielectric layer is formed over the substrate. Next, a node contact opening through the dielectric layer to top surface of the substrate is formed by coating the dielectric layer with a photoresist layer, patterning the photoresist layer with pattern of a node contact by exposure and development, then etching the dielectric layer until top surface of said substrate exposed using said patterned photoresist layer as a mask. Subsequently, the photoresist layer is removed. Finally, a silicon nitride layer is formed on inside wall of the node contact opening by rapid thermal chemical vapor deposition (RTCVD).

Abstract: A method for manufacturing a semiconductor device is disclosed. The method can reduce thermal budget in node contact application. It includes mainly the following processes. A substrate is first provided, then a dielectric layer is formed over the substrate. Next, a node contact opening through the dielectric layer to top surface of the substrate is formed by coating the dielectric layer with a photoresist layer, patterning the photoresist layer with pattern of a node contact by exposure and development, then etching the dielectric layer until top surface of said substrate exposed using said patterned photoresist layer as a mask. Subsequently, the photoresist layer is removed. Finally, a silicon nitride layer is formed on inside wall of the node contact opening by rapid thermal chemical vapor deposition (RTCVD).

Abstract: A method for forming MOSFET is disclosed. The method includes firstly providing a substrate, on which a gate without spacer is already formed. A first spacer is formed on sidewall of the gate, a lightly doped drain is subsequently formed in the substrate. Next, a second spacer is formed on the first spacer. Finally, a heavily doped drain is formed in the substrate. The present invention can enhance stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract: An ornamental display toy, which includes a transparent container supported on a base and filled with a chemical liquid, a magnetic stirrer mounted in the container and driven to stir up the liquid, a motor drive formed of a motor and a transmission mechanism and controlled by a control circuit to turn the magnetic stirrer on its own axis and to revolve the magnetic stirrer around the longitudinal central axis of the container, causing a variable whirlpool to be produced in the liquid inside the container.

Abstract: A fluid-filled light apparatus comprises a two-tube transparent container which provides light and produces distinct visual effects. The two-tube transparent container comprises an inner transparent tube suspended within an outer transparent tube. First terminal ends of each of the transparent tubes is sealed by a transparent tube cap which suspends the inner transparent tube within the outer transparent tube. A second terminal end of the outer transparent tube attaches the transparent tubes as one assembly to a base member. Each transparent tube holds liquid and decorative objects. The base member includes a motor, a power supply and an illuminating unit.

Abstract: A method for forming a transistor in integrated circuits is disclosed. The method includes the following steps. A substrate is first provided. An insulating layer is then formed on the substrate. A conductor layer is formed on the insulating layer. Subsequently, a patterned photoresist layer is formed on the conductor layer. Next, an etch process is used to etch the conductor layer which has a sidewall. The patterned photoresist layer is then removed. After forming a liner layer on the sidewall of the conductor layer, a lightly doped drain is formed on and in the substrate. Then, a spacer is formed on the liner layer. Thereafter, a proper process is used to introduce ions into the lightly doped drain, and then a source/drain region is completed. The steps with follow include annealing the source/drain region and removing the spacer. Subsequently, an epi-silicon layer is formed on the lightly doped drain region, the source/drain region and the top surface of the conductor layer.

Abstract: In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.

Abstract: A method for fabricating a landing pad is described in which a transistor is formed on the substrate, wherein the transistor comprises a gate and source/drain regions at both sides of the gate in the substrate. A cap layer and a spacer are formed on the gate and at the sidewall of the gate respectively. A protective layer is formed to cover the substrate. The protective layer is then defined to form an opening to expose the source/drain region. A polysilicon landing pad is then formed in the opening and on the protective layer at the periphery of the opening. Silicidation is then conducted on the polysilicon landing pad to form a metal silicide landing pad and to destroy any native oxide at the source/drain region.

Abstract: A method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. Metal oxide semiconductors and source/drain regions are respectively formed in the memory region and in the logic region. A defined dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region until the source/drain regions are exposed. Silicide layers are formed over the contact holes. Portions of the silicide layer extend to surface of the dielectric layer neighboring the contact holes. A defined inter-layer dielectric layer is formed over the substrate. Vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. The self-aligned contact is formed.

Abstract: A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.