Abstract: Systems and methods are provided for a single phase clock controlled flip flop circuit. The circuit comprises a single phase master latch that is configured to receive a data signal and a first timing signal having a first phase. The circuit is configured to generate a master latch output signal based on the data signal and the first timing signal. The single phase master latch is not configured to receive a second timing signal having a second phase. The circuit further includes a slave latch coupled to the single phase master latch. The slave latch is configured to receive the master latch output signal, to store digital data based on the master latch output signal, and to generate a flip flop output signal based on the master latch output signal.

Abstract: A wireless communication device includes a casing having a wireless signal penetrating area, an antenna sending a wireless signal through the wireless signal penetrating area, and an electromagnetic lens assembly including a lens barrel and a lens. The lens barrel has a first end and a second end. The first end is closer to the wireless signal penetrating area than the second end. The lens disposed in the lens barrel has an incident surface and an emission surface on an axis of the lens. The incident surface is a flat surface facing the first end. The emission surface is a convex surface and has a curvature, which is not equal to 0, from a perspective of a first axis perpendicular to the axis of the lens, and has a curvature of 0 from a perspective of a second axis perpendicular to the axis of the lens and the first axis.

Abstract: An IC device manufacturing method includes forming first and second active areas in a first row extending in a first direction and third and fourth active areas in a second, adjacent row, each including S/D structures, constructing first and second conductive segments extending in a second direction overlying and electrically connected to a S/D structure in each of the second and third active areas, constructing additional conductive segments, gates, and vias to form an AOI, OAI, or four-input NAND including the first and second segments and pull-up and pull-down transistors in each of the first and second rows, and constructing first through third power rails extending in the first direction, the first and second and second and third power rails aligned with the respective first and second rows. The first and second segments cross a plane perpendicular to the first and second conductive segments and including the second power rail.

Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.

Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.

Abstract: A button module includes a first electronic element, a pressing element, a second electronic element, and an operation element. The pressing element has a pressing part and a first actuation part. The pressing part has a through-hole. The pressing part moves relative to the first electronic element in a pressing direction. The pressing part drives the first actuation part to move when the pressing part moves so that the first actuation part actuates the first electronic element. The operation element has a driven part and a second actuation part. The second actuation part actuates the second electronic element. The driven part moves relative to the pressing part in an operation direction. The driven part drives the second actuation part to move when the driven part moves so that the second actuation part actuates the second electronic element. A projection device with the button module is also provided.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A cable assembly and a cable connection component are provided. The cable assembly includes a cable and a cable connection component. The cable connection component includes a first outer metal member, a second outer metal member and a holding component. The second outer metal member has an end for interlocking with an end of the first outer metal member. The holding component is disposed between the first outer metal member and the second outer metal member. The holding component includes two inner metal members that are fixed to each other by a fixing member. Each inner metal member includes a wire slot, the wire slot includes an end section and two branch sections, the two end sections jointly hold a portion of the cable in place, and each branch section of the two inner metal members jointly hold one of core wires of the cable in place.

Abstract: A device is disclosed that includes multiple channels and multiple processing nodes. Each processing node includes input/output (I/O) ports coupled to the channels and channel control modules coupled to the I/O ports. Each processing node is configured to select, by the channel control module in a first operation, a first I/O port of the I/O ports; communicate a first message, via the first I/O port, to a first processing node over a first channel or a second processing node over a second channel orthogonal to the first channel in a logic representation; select, by the channel control module in a second operation, a second I/O port of the I/O ports; and communicate a second message, via the second I/O port, to a third processing node over a third channel extending in a diagonal direction and non-orthogonal to the first and second channels in the logic representation.

Abstract: A data retention circuit includes a flip-flop circuit including a master latch coupled to a slave latch, wherein the slave latch includes a first input terminal and a first output terminal, and a series combination of a retention latch and a level shifter coupled between the first input terminal and the first output terminal. The slave latch is configured to be selectively coupled to the series combination through a first transmission gate responsive to a restore signal.

Abstract: Methods for formation of a layer stack during a back-end-of-line (BEOL) process flow and the layer stack formed therefrom are provided. In one or more embodiments, the method utilizes a two-dimensional (2D) self-aligned scheme with a subtractive metal etch. The method includes using a hard mask to form a via with a small width which is formed through or contacts each of a first metal layer and a second metal layer. The via is filled with a metal gapfill to connect the first metal layer and the second metal layer. Each of the first metal layer and the second metal layer are patterned to form a plurality of features.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type; a well region of the first conductivity type in the semiconductor substrate; and a fin disposed on the semiconductor substrate within the well region. The fin extends along a first direction. The fin includes a first portion and a second portion that is contiguous with the first portion. The first portion includes a counter-doping region having dopants of a second conductivity type. A gate extends over the fin along a second direction. The gate overlaps with the first portion of the fin and does not overlap with the second portion of the fin.

Abstract: Systems, methods, and devices for a ball grid array with non-linear conductive routing are described herein. Systems include a printed circuit board, a microprocessor, a ball grid array, and a substrate. The ball grid array includes a first solder ball and a second solder ball. The substrate includes a non-linear conductive routing electrically coupling the first solder ball and the second solder ball. The non-linear conductive routing includes a first routing section connected to the first solder ball, and a second routing section connected to the second solder ball. The non-linear conductive routing further includes a third routing section connected to the first routing section, and a fourth routing section connected to the third routing section, wherein each of the third routing section and the fourth routing section are rotational routing sections configured to flow current in a first rotational direction.

Abstract: Methods for determining suitability of Czochralski growth conditions to produce silicon substrates for epitaxy. The methods involve evaluating substrates sliced from ingots grown under different growth conditions (e.g., impurity profiles) by imaging the wafer by infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters may be compared to determine which growth conditions are well-suited to produce substrates for epitaxial and/or post-epi heat treatments.

Abstract: A machine-learning apparatus includes: a learning-data storage section that stores plural sets of learning data including input data and output data, the input data including shape parameters of a pump section having an impeller and a flow passage section in which the impeller is accommodated, the output data including pump performance of a pump having the pump section defined by the shape parameters; a machine-learning section configured to cause a learning model to learn a correlation between the input data and the output data by inputting the plural sets of the learning data to the learning model; and a learned-model storage section configured to store the learning model that has been caused to learn the correlation by the machine-learning section.

Abstract: An IC device includes first and second power rails extending in a first direction and carrying one of a power supply or reference voltage, a third power rail extending between the first and second power rails and carrying the other of the power supply or reference voltage, and a plurality of transistors including first through fourth active areas extending between the first and second power rails, a plurality of gate structures extending perpendicularly to the first direction, and first and second conductive segments extending in the second direction across the third power rail. Each of the second and third active areas is adjacent to the third power rail, each of the first and second conductive segments is electrically connected to S/D structures in each of the second and third active areas, and the plurality of transistors is configured as one of an AOI, an OAI, or a four-input NAND gate.

Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.

Abstract: Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may further include performing an ion etch to the opening by delivering an ion beam at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etch comprises a lean-gas chemistry, and wherein the ion etch causes the layer of the semiconductor device to be removed faster along the set of curved sections than along the set of sidewalls.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.