Patents by Inventor Yung Chen

Yung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240302581
    Abstract: An opto-electronic device to distribute an ultra-wide field of illumination is disclosed. In examples, the electronic device includes an optical source to generate light and a diffuser to receive and distribute the light. The diffuser includes a plurality of extensions, each having a reflective surface arranged at an angle to cause total internal reflection of an incident light ray, and an exit surface arranged at an angle relative to the reflective surface and configured to direct the light ray at one or more transmission angles different from an incident angle.
    Type: Application
    Filed: March 9, 2023
    Publication date: September 12, 2024
    Inventors: Pei-Song Cai, Jason O'Daniel, Hong-Zhi Liu, Francesco Schiattone, Yi-Yung Chen
  • Publication number: 20240293282
    Abstract: An apparatus for generating an acoustic energy pulse and delivering it into a body is described. The apparatus includes a generator for creating an acoustic energy pulse having an energy density field that can be measured at all points within a space in the shape of an imaginary cylinder having a length greater than or equal to 2 cm and a diameter. The cylindrically shaped space has a cylinder longitudinal axis oriented relative to a longitudinal axis of the energy pulse at an angle in the range from zero to twenty degrees. A minimum energy density for the pulse at all locations within the cylindrically shaped space is at least 50% of a maximum energy density for the pulse within the space.
    Type: Application
    Filed: May 14, 2024
    Publication date: September 5, 2024
    Inventors: Charles R. Engles, Yung Chen Su
  • Patent number: 12081215
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lun Ou, Ji-Yung Lin, Yung-Chen Chien, Ruei-Wun Sun, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
  • Publication number: 20240290709
    Abstract: Systems, methods, and devices for a ball grid array with non-linear conductive routing are described herein. Such a ball grid array may include a plurality of solder balls that are electrically coupled by a non-linear conductive routing. The non-linear conductive routing may include a plurality of routing sections where each of the plurality of routing sections is disposed at an angle to adjacent routing sections.
    Type: Application
    Filed: March 5, 2024
    Publication date: August 29, 2024
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chenxi Huang, Yung Chen
  • Patent number: 12074069
    Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang, Tzu-Ying Lin
  • Publication number: 20240277865
    Abstract: Disclosed herein is a phage-displayed single-chain variable fragment (scFv) library, which comprises a plurality of phage-displayed scFvs characterized with a specific sequence in each CDR. The present phage-displayed scFv library is useful in selecting an antibody fragment exhibiting a binding affinity and specificity to mesothelin (MSLN). Also disclosed herein are a recombinant antibody specific to MSLN, an immunoconjugate comprising the recombinant antibody, and uses thereof in treating cancers.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 22, 2024
    Inventors: An-Suei YANG, Hung-Ju HSU, Chao-Ping TUNG, Chung-Ming YU, Chi-Yung CHEN, Hong-Sen CHEN, Yu-Chuan HUANG, Pei-Hsun TSAI, Szu-Yu LIN, Hung-Pin PENG
  • Patent number: 12066489
    Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Johnny Chiahao Li, Sheng-Hsiung Chen, Tzu-Ying Lin, Yung-Chen Chien, Jerry Chang Jui Kao, Xiangdong Chen
  • Patent number: 12061232
    Abstract: A margin tester including an identification reader configured to receive an adaptor identifier of an adaptor, an interface configured to connect to a device under test through the adaptor, and one or more processors configured to assess a margin, such as an electrical margin or an optical margin, of a device under test and tag the assessment with the adaptor identifier. Assessing the margin can include assessing the margin based on an expected margin that is predicted or provided based on the adaptor identifier.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: August 13, 2024
    Assignee: Tektronix, Inc.
    Inventors: Sam J. Strickling, Daniel S. Froelich, Michelle L. Baldwin, Jonathan San, Lin-Yung Chen
  • Patent number: 12055603
    Abstract: A cable structured to be repeatedly connected to a device, each repeated connection causing degradation of the cable, the cable including a condition indicator disposed on the cable and configured to be updated with each successive connection of the cable into the device.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: August 6, 2024
    Assignee: Tektronix, Inc.
    Inventors: Sam J. Strickling, Daniel S. Froelich, Michelle L. Baldwin, Jonathan San, Lin-Yung Chen
  • Publication number: 20240250671
    Abstract: An integrated circuit (IC) device includes a master latch circuit having a data output, a slave latch circuit having a data input electrically coupled to the data output of the master latch circuit, and a clock circuit electrically coupled to the master latch circuit and the slave latch circuit. The slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.
    Type: Application
    Filed: April 2, 2024
    Publication date: July 25, 2024
    Inventors: Cheng-Yu LIN, Yung-Chen CHIEN, Jia-Hong GAO, Jerry Chang Jui KAO, Hui-Zhong ZHUANG
  • Publication number: 20240251150
    Abstract: Transmission assemblies to project illumination from an edge of an electronic device are disclosed. In some examples, the transmission assemblies include an optical source to generate laser light. An optical focusing element to focus the laser light. And a transmitting optical element is arranged at a bezel proximate an external edge of the electronic device.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 25, 2024
    Inventors: Pei-Song Cai, Hong-Zhi Liu, Jason O'Daniel, Francesco Schiattone, Yi-Yung Chen
  • Patent number: 12047079
    Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chen Chien, Xiangdong Chen, Hui-Zhong Zhuang, Tzu-Ying Lin, Jerry Chang Jui Kao, Lee-Chung Lu
  • Publication number: 20240240355
    Abstract: Methods for producing single crystal silicon wafers for use in insulated gate bipolar transistors are disclosed. The methods may involve determining the radial profile of a ratio between (i) a growth velocity, v, and (ii) an axial temperature gradient, G for an ingot with relatively low oxygen. Based on the radial v/G profile, a nitrogen concentration which widens the v/G window to produce Perfect Silicon free of COP and gate oxide failures may be selected.
    Type: Application
    Filed: January 12, 2024
    Publication date: July 18, 2024
    Inventors: Carissima Marie Hudson, JaeWoo Ryu, Chi-Yung Chen, Chih-Hsun Wei, Feng-Chien Tsai, Chung-Chi Hsiao
  • Publication number: 20240244786
    Abstract: A server apparatus includes a bottom board, a tray, a host device disposed on the tray and having a first connector, and an elastic piece. A pin protrudes from the bottom board and is inserted into a hole of the tray to make the tray movably connected on the bottom board. The elastic piece includes an elastic arm and a body connected on the tray. The elastic arm extends from the body to pass through a slot of the tray, so as to abut against the bottom board for supporting the tray above the bottom board when the tray is connected on the bottom board. Therefore, the tray can move a first distance relative to the bottom board.
    Type: Application
    Filed: May 11, 2023
    Publication date: July 18, 2024
    Applicant: Wistron Corporation
    Inventor: Yung-Chen Chen
  • Patent number: 12040800
    Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien
  • Publication number: 20240231202
    Abstract: A projection device provided includes a projector housing and a protective sleeve. At least one magnetic element is disposed on an outer surface of the projector housing. The protective sleeve is adapted to cover the projector housing. The protective sleeve includes a body and a magnetic attraction module, and the magnetic attraction module is disposed at a first end of the body. The protective sleeve has the advantages of easy disassembly and assembly.
    Type: Application
    Filed: December 25, 2023
    Publication date: July 11, 2024
    Inventors: CHIEN-CHUNG LIAO, CHANG-YUNG CHEN, CHUN-HSIEN WU
  • Patent number: 12016817
    Abstract: An apparatus for generating an acoustic energy pulse and delivering it into a body is described. The apparatus includes a generator for creating an acoustic energy pulse having an energy density field that can be measured at all points within a space in the shape of an imaginary cylinder having a length greater than or equal to 2 cm and a diameter. The cylindrically shaped space has a cylinder longitudinal axis oriented relative to a longitudinal axis of the energy pulse at an angle in the range from zero to twenty degrees. A minimum energy density for the pulse at all locations within the cylindrically shaped space is at least 50% of a maximum energy density for the pulse within the space.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: June 25, 2024
    Assignee: Acoustic Wave Cell Therapy, Inc.
    Inventors: Charles R. Engles, Yung Chen Su
  • Patent number: 12018400
    Abstract: A system for producing a silicon ingot, the system includes a crystal puller, a pyrometer, an infrared (IR) camera, and a controller. The crystal puller includes a hot zone having one or more components therein, and in which a silicon ingot may be pulled. The pyrometer is positioned to view a region of interest within the hot zone. The IR camera is positioned to view one or more additional regions of interest within the hot zone. The controller is connected to the crystal puller, the pyrometer, and the IR camera. The controller is programmed to control the crystal puller to produce a silicon ingot, receive temperature data of the region of interest within the hot zone from the pyrometer while producing the silicon ingot, and receive IR images of the one or more additional regions of interest from the IR camera while producing the silicon ingot.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: June 25, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Zheng Lu, Chi-Yung Chen, Hsien-Ta Tseng, Sumeet S. Bhagavat, Vahid Khalajzadeh
  • Patent number: 12020908
    Abstract: Embodiments of the present disclosure generally relate to methods for etching materials. In one or more embodiments, the method includes positioning a substrate in a process volume of a process chamber, where the substrate includes a metallic ruthenium layer disposed thereon, and exposing the metallic ruthenium layer to an oxygen plasma to produce a solid ruthenium oxide on the metallic ruthenium layer and a gaseous ruthenium oxide within the process volume. The method also includes exposing the solid ruthenium oxide to a secondary plasma to convert the solid ruthenium oxide to either metallic ruthenium or a ruthenium oxychloride compound. The metallic ruthenium is in a solid state on the metallic ruthenium layer or the ruthenium oxychloride compound is in a gaseous state within the process volume.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: June 25, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yung-chen Lin, Chi-I Lang, Ho-yung Hwang
  • Publication number: 20240201727
    Abstract: A clock distribution system includes a clock mesh structure which has first metal patterns extending along a first axis, second metal patterns extending along a second axis, third metal patterns extending along a third axis. The first metal patterns, second metal patterns, and third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis. The first metal patterns include a main first metal pattern, and other first metal patterns. The second metal patterns include a main second metal pattern, and other second metal patterns. The third metal patterns include a main third metal pattern, and other third metal patterns.
    Type: Application
    Filed: February 1, 2024
    Publication date: June 20, 2024
    Inventors: Jerry Chang Jui KAO, Huang-Yu CHEN, Sheng-Hsiung CHEN, Jack LIU, Yung-Chen CHIEN, Wei-Hsiang MA, Chung-Hsing WANG