Patents by Inventor Yung-Cheng Lin

Yung-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7652534
    Abstract: A rail-to-rail operational amplifier capable of reducing current consumption includes an amplification stage circuit including a first compensation output terminal and a second compensation output terminal, for generating an amplified signal according to an input signal, an output stage circuit coupled to the amplification stage circuit, for outputting the amplified signal, and a compensation circuit coupled to the amplification stage circuit and the output stage circuit. The compensation circuit includes a first voltage generator for generating a first voltage, a second voltage generator for generating a second voltage, a first compensation capacitor, a second compensation capacitor, and four switches named from a first switch to a fourth switch, wherein the first voltage is approximately a steady state voltage of the first compensation output terminal and the second voltage is approximately a steady state voltage of the second compensation output terminal.
    Type: Grant
    Filed: November 2, 2008
    Date of Patent: January 26, 2010
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chia-Hung Lin, Jr-Ching Lin, Yung-Cheng Lin, Tsung-Hau Chang
  • Publication number: 20090085654
    Abstract: A biasing circuit includes a reference current source, a first transistor, a second transistor, and a voltage buffer. The first transistor includes a first connection end coupled to the reference current source, a control end, and a second connection end coupled to a system grounding end. The second transistor includes a control end coupled to the control end of the first transistor, a first connection end coupled to a system power supply end, and a second connection end coupled to the system grounding end. The voltage buffer includes an input end coupled to an output end of the reference current source and the first connection end of the first transistor, and an output end coupled to the control ends of the first transistor and the second transistor. The first transistor and the second transistor constitute a current mirror.
    Type: Application
    Filed: February 4, 2008
    Publication date: April 2, 2009
    Inventor: Yung-Cheng Lin
  • Patent number: 5887309
    Abstract: A sponge mop is composed of a handle, a lever, a rotary sleeve, a socket, a mophead seat, a sponge body, and two link rods. The lever and the mophead seat are connected by the two link rods. The lever is fastened pivotally with the handle which is in turn engaged at one end thereof with the rotary sleeve. The rotary sleeve is engaged at another end thereof with the socket which is in turn engaged at another end thereof with the mophead seat. As the rotary sleeve is rotated, the link rods are actuated by the handle to enable the mophead seat to swivel.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: March 30, 1999
    Inventor: Yung-Cheng Lin
  • Patent number: 5794302
    Abstract: A car washing brush is composed of a head, a holding plate, and a handle. The head is held by the holding plate and is provided with the bristles attached thereto securely for bringing about the brushing effect. The handle is fastened pivotally at one end thereof with the holding plate by a fastening device enabling the handle to be rotated in relation to the holding plate at such time when a press button of the handle is pressed by the finger of a person using the washing brush. The extension of the handle is therefore attained.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: August 18, 1998
    Inventor: Yung-Cheng Lin
  • Patent number: 5761718
    Abstract: An algorithm for conditionally pre-fetching data for DRAM access is disclosed. A similar pattern of performing successive block reads of DRAM data in the execution of several types of instructions in a computer system is determined by analyzing CPU signals. These instructions repeatedly read blocks of data from a local memory area. Additional writes to memory or an input/output port may intervene between the repeated block reads. By using the pattern as a condition for pre-fetching data from DRAM into a high speed memory buffer of a memory controller, consecutive memory reads can be completed with zero wait state. The penalty incurred by unconditional pre-fetching of DRAM data is minimized. The conditional pre-fetching mechanism is applicable to other computer peripheral devices.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: June 2, 1998
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Yung Cheng Lin, Shih Jen Chuang