Patents by Inventor Yung-Ching Hsieh

Yung-Ching Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210274279
    Abstract: A display including a front frame, a rear case, a display panel and a sound emitting device is provided. The display panel is disposed between the front frame and the rear case, and a display surface of the display panel is exposed from the front frame. The sound emitting device is disposed between the front frame and the rear case and includes a sound box, a speaker unit and a sound guide channel. The speaker unit disposed on the sound box has a sound emitting surface facing a first direction. The sound guide channel is extended to the sound emitting surface and has a sound outlet facing a second direction. The first direction is not parallel to the second direction.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 2, 2021
    Applicant: Qisda Corporation
    Inventors: Yung-Chun SU, Weng-Ching HSIEH, Chung-Hao YANG, Hung-Mao CHEN
  • Publication number: 20210183944
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.
    Type: Application
    Filed: January 20, 2020
    Publication date: June 17, 2021
    Inventors: Yi-Ting Wu, Jian-Jhong Chen, Po-Chun Yang, Jhen-Siang Wu, Yung-Ching Hsieh, Bo-Chang Li, Jen-Yu Wang, Cheng-Tung Huang
  • Patent number: 11018185
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: May 25, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Jian-Jhong Chen, Po-Chun Yang, Jhen-Siang Wu, Yung-Ching Hsieh, Bo-Chang Li, Jen-Yu Wang, Cheng-Tung Huang
  • Patent number: 10978122
    Abstract: A memory includes (n?1) non-volatile cells, (n?1) bit lines and a current driving circuit. Each of the (n?1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n?1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n?1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n?1) non-volatile cells.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Ya-Lan Chiou, Chun-Hsien Huang, Chih-Wei Tsai, Hsin-Chih Yu, Yi-Ting Wu, Cheng-Tung Huang, Jen-Yu Wang, Jhen-Siang Wu, Po-Chun Yang, Yung-Ching Hsieh, Jian-Jhong Chen, Bo-Chang Li
  • Patent number: 10651235
    Abstract: A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 12, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Jhen-Siang Wu, Po-Chun Yang, Yung-Ching Hsieh, Zong-Sheng Zheng, Jian-Jhong Chen, Jen-Yu Wang, Cheng-Tung Huang
  • Patent number: 9679622
    Abstract: A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: June 13, 2017
    Assignee: Piecemakers Technology, Inc.
    Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Yung-Ching Hsieh
  • Publication number: 20150287445
    Abstract: A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 8, 2015
    Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Yung-Ching Hsieh
  • Publication number: 20060087013
    Abstract: An electronic package assembly is formed with a plurality of integrated circuit dies stacked in layers. At least one first die is placed on a substrate. Each subsequent layer of the stack contains at least one die. Each die on each layer has a size and shape such that, when placed on the dies on a lower layer, it is offset from the edges of the dies on the lower layer to allow affixing of wirebonds to input/output pads of the dies on the lower layer. Each die on each layer with more than one die has input/output pads placed on two sides of the die. Each die on an upper layer is placed orthogonally to each die of a lower each layer such that wirebonds are affixed without interference.
    Type: Application
    Filed: October 21, 2004
    Publication date: April 27, 2006
    Inventor: Yung-Ching Hsieh
  • Patent number: 5801997
    Abstract: A reciprocating or ping-pong voltage boosting circuit is described. The ping-pong boosting circuit has a first and a second boost circuit connected between the power supply voltage source and a ground reference point to generate a first instance and a second instance of a boost voltage. The reciprocating circuit has a switching circuit to alternately place the first and second instance of the boost voltage upon the signal line to bring the voltage level of the signal line to that of the boost voltage. A boost control circuit will provide a switching signal that will control the alternate placing of the first and second instances of the boost voltage upon the signal line. The boost control circuit will provide a boost signal that will cause the first and second boost circuits to generate the first and second instances of the boost voltage.
    Type: Grant
    Filed: June 24, 1997
    Date of Patent: September 1, 1998
    Assignee: Etron Technology, Inc.
    Inventors: Chung-Wei Hsieh, Yung-Ching Hsieh, Tah-Kang Joseph Ting
  • Patent number: 5754479
    Abstract: The invention describes a technique in which the performance of a block write operations for SGRAM and VRAM are improved. The technique also produces improved noise margin along the data line when connecting to bit switches under mask during block write operation. The technique rearranges the physical location of each bit switch located along the data lines such that the worse case configuration is not clustered at the end of the data lines during a block write operation. This reduces the voltage drop along the data lines and provides more energy to switch bit lines or the corresponding memory columns. It also produces less drop on the bit lines as a result of doing a mask during the block write operation.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: May 19, 1998
    Assignee: Etron Technology, Inc.
    Inventors: Tah-Kang Joseph Ting, Yung-Ching Hsieh, Chun Shiah
  • Patent number: 5737271
    Abstract: Circuits and methods are disclosed for a row activation control logic for memory arrays. This invention utilizes a row activation control circuit and a NOR gate, in conjunction with a previously disclosed timing reference circuit, to allow the shortening of the row precharge time, yet insuring that the bitline is getting charged well enough without causing the chip to read wrong data at the next row activation. The circuits and methods disclosed can be applied to different types of dynamic random access memories.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: April 7, 1998
    Assignee: Etron Technology, Inc.
    Inventors: Tah-Kang Joseph Ting, Bor-Doou Rong, Yung-Ching Hsieh
  • Patent number: 5689200
    Abstract: A high speed clock-positive edge detection circuit with chip select control that produces a glitch-free transition detection pulse is described. The circuit comprises Logic, Conditioning and Output Sections. An n-channel transistor is connected between output C, output B and the Chip Select input. This eliminates glitches that would otherwise be present, as in the prior art.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: November 18, 1997
    Assignee: Etron Technology, Inc.
    Inventors: Tah-Kang Joseph Ting, Jeng-Tzong Shih, Yung-Ching Hsieh
  • Patent number: 5506815
    Abstract: A buffer memory system provides independent memory blocks, each with independent addressing and data paths, for a processor and input and output devices. The processor can configure the data paths so that an input device can initially supply data to a first memory block. The processor can then assign a second block for input and operate on the data in the first block. The processor can store the results of the process in a third block that has been assigned to an output device. The memory blocks and the associated data paths can paired for operating with a processor with a wider data bus.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: April 9, 1996
    Assignee: Etron Technology Inc.
    Inventors: Yung-Ching Hsieh, Yin H. Lieu