Patents by Inventor YUNG CHUN LI

YUNG CHUN LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250191621
    Abstract: A page buffer circuit adapted for a page-read device which including a memory array having several pages and several bit lines. The page buffer circuit comprises the following elements. First latches, receive a weight-vector from a corresponding one of the pages through the bit lines, and import an input-vector through a data input/output path. The weight-vector has a plurality of weight bit-data, and the input-vector has a plurality of input bit-data. Second latches, store the input bit-data of the input-vector. Logic operation units, coupled to the first latches to receive the weight bit-data, and coupled to the second latches to receive the input bit-data, perform a logic operation of the input bit-data and the weight bit-data to generate a logic operation result. The logic operation result is sent to one the first latches. A control circuit, selectively enables the logic operation units to perform the logic operation.
    Type: Application
    Filed: December 11, 2023
    Publication date: June 12, 2025
    Inventors: Bo-Rong LIN, Han-Wen HU, Yung-Chun LI, Huai-Mu WANG
  • Patent number: 12314261
    Abstract: A filtered search method, for performing a search within a data set, and the data set includes several data points. The filtered search method includes the following steps. Dividing the data set into several clusters based on a similarity of the data points. Dividing each of the clusters into an inlier part and an outlier part based on a distribution density of the data points. Performing a coarse search on all of the inlier parts, to filter out inlier parts of a first candidate number. Performing a fine search on the inlier parts of the first candidate number, to search data points of a second candidate number. Obtaining a search result based on the data points of the second candidate number, and the data points of the second candidate number are close to a target point.
    Type: Grant
    Filed: May 6, 2024
    Date of Patent: May 27, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Huai Shih, Han-Wen Hu, Huai-Mu Wang, Yung-Chun Li
  • Publication number: 20250165407
    Abstract: Systems, devices, methods, and circuits for managing data security in storage devices. In one aspect, a storage device includes at least one memory device and a controller coupled to the at least one memory device. The controller is configured to: encrypt first data with a first type of cryptographic algorithm and encrypt second data with a second type of cryptographic algorithm. The first data is associated with a first security level, and the second data is associated with a second security level that is higher than the first security level. The second type of cryptographic algorithm has a greater encryption strength than the first type of cryptographic algorithm.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 22, 2025
    Applicant: Macronix International Co., Ltd.
    Inventors: Yu-Ming Huang, Chih-Huai Shih, Yung-Chun Li
  • Publication number: 20250157548
    Abstract: The disclosure discloses a memory device and an operation method thereof. A target memory cell and at least one replicated memory cell belonging to the same memory string are selected. A target weight value written into the target memory cell is replicated to the at least one replicated memory cell, wherein the target memory cell and the at least one replicated memory cell store the target weight value. In response to a command of reading or computing on the target memory cell received by the memory device, reading or computing is performed on the target memory cell and the at least one replicated memory cell simultaneously.
    Type: Application
    Filed: March 20, 2024
    Publication date: May 15, 2025
    Inventors: Huai-Mu WANG, Han-Wen HU, Yung-Chun LI, Chih-Chang HSIEH, Shang-Ting LIN
  • Publication number: 20250156420
    Abstract: A filtered search method, for performing a search within a data set, and the data set includes several data points. The filtered search method includes the following steps. Dividing the data set into several clusters based on a similarity of the data points. Dividing each of the clusters into an inlier part and an outlier part based on a distribution density of the data points. Performing a coarse search on all of the inlier parts, to filter out inlier parts of a first candidate number. Performing a fine search on the inlier parts of the first candidate number, to search data points of a second candidate number. Obtaining a search result based on the data points of the second candidate number, and the data points of the second candidate number are close to a target point.
    Type: Application
    Filed: May 6, 2024
    Publication date: May 15, 2025
    Inventors: Chih-Huai SHIH, Han-Wen HU, Huai-Mu WANG, Yung-Chun LI
  • Publication number: 20250158628
    Abstract: An analog-to-digital conversion device, includes the following elements. A sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value. A latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value. The latches and the logic circuits are used to perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.
    Type: Application
    Filed: June 7, 2024
    Publication date: May 15, 2025
    Inventors: Han-Wen HU, Yung-Chun LI, Chih-Chang HSIEH, BO-RONG LIN, Huai-Mu WANG, Chih-Huai SHIH
  • Publication number: 20250157508
    Abstract: The application discloses a memory device and a computation method thereof. A plurality of weight data are stored in a plurality of first memory cells of the memory device. A plurality of input data are input via a plurality of string select lines. A plurality of memory cell currents are generated in the plurality of first memory cells based on the weight data and the input data. The memory cell currents are summed on a plurality of bit lines coupled to the plurality of string select lines to obtain a plurality of summed currents. The summed currents are converted into a plurality of analog-to-digital conversion results. The plurality of analog-to-digital conversion results are accumulated to obtain a computational result.
    Type: Application
    Filed: April 22, 2024
    Publication date: May 15, 2025
    Inventors: Huai-Mu WANG, Han-Wen HU, Yung-Chun LI, Bo-Rong LIN
  • Patent number: 12260130
    Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: March 25, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hang-Ting Lue, Tzu-Hsuan Hsu, Teng-Hao Yeh, Chih-Chang Hsieh, Chun-Hsiung Hung, Yung-Chun Li
  • Patent number: 12169702
    Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: December 17, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Bo-Rong Lin, Yung-Chun Li, Han-Wen Hu, Huai-Mu Wang
  • Publication number: 20240386958
    Abstract: The application provides a content addressable memory (CAM) device and a method for searching and comparing data thereof. The CAM device comprises: a plurality of memory strings; and a sensing amplifier circuit coupled to the memory strings; wherein in data searching, a search data is compared with a storage data stored in the memory strings, the memory strings generate a plurality of string currents, the sensing amplifier circuit senses the string currents to generate a plurality of sensing results; based on the sensing results, a match degree between the search data and the storage data is determined as one of the follows: all-matched, partially-matched and all-mismatched.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Po-Hao TSENG, Yu-Hsuan LIN, Feng-Min LEE, Yung-Chun LI
  • Patent number: 12020747
    Abstract: A non-volatile memory and a programming method thereof are provided. The programming method of the non-volatile memory includes the following steps. A coarse programming procedure is performed for programing all of a plurality of memory cells at an erase state to 2{circumflex over (?)}N?1 or 2{circumflex over (?)}N program states. N is a positive integer. A fine programming procedure is performed for pushing all of memory cells into 2{circumflex over (?)}N?1 or 2{circumflex over (?)}N verify levels.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: June 25, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Feng-Min Lee, Yung-Chun Li
  • Patent number: 11966628
    Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 23, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11955199
    Abstract: A memory chip, a memory device and an operation method are disclosed. The memory chip includes a number of memory units and a control logic circuit. The memory units could be configured as TLC, MLC or SLC. The control logic circuit is configured to use TLC programming approach to program MLC and SLC.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: April 9, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Chun Li, Yu-Ming Huang
  • Patent number: 11914887
    Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 27, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Chun Li, Han-Wen Hu, Bo-Rong Lin, Huai-Mu Wang
  • Publication number: 20240028211
    Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.
    Type: Application
    Filed: January 31, 2023
    Publication date: January 25, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Hang-Ting Lue, Tzu-Hsuan Hsu, Teng-Hao Yeh, Chih-Chang Hsieh, Chun-Hsiung Hung, Yung-Chun LI
  • Publication number: 20230410856
    Abstract: A memory chip, a memory device and an operation method are disclosed. The memory chip includes a number of memory units and a control logic circuit. The memory units could be configured as TLC, MLC or SLC. The control logic circuit is configured to use TLC programming approach to program MLC and SLC.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Inventors: Yung-Chun LI, Yu-Ming HUANG
  • Publication number: 20230238037
    Abstract: The application provides a content addressable memory (CAM) memory device and a method for searching and comparing data thereof. The CAM memory device comprises: a plurality of CAM memory strings; and a sensing amplifier circuit coupled to the CAM memory strings; wherein in data searching, a search data is compared with a storage data stored in the CAM memory strings, the CAM memory strings generate a plurality of memory string currents, the sensing amplifier circuit senses the memory string currents to generate a plurality of sensing results: based on the sensing results, a match degree between the search data and the storage data is determined as one of the follows: all-matched, partially-matched and all-mismatched.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 27, 2023
    Inventors: Po-Hao TSENG, Yu-Hsuan LIN, Feng-Min LEE, Yung-Chun LI
  • Publication number: 20230221882
    Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
    Type: Application
    Filed: June 2, 2022
    Publication date: July 13, 2023
    Inventors: Wei-Chen WANG, Han-Wen HU, Yung-Chun LI, Huai-Mu WANG, Chien-Chung HO, Yuan-Hao CHANG, Tei-Wei KUO
  • Publication number: 20230221956
    Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.
    Type: Application
    Filed: June 2, 2022
    Publication date: July 13, 2023
    Inventors: Wei-Chen WANG, Han-Wen HU, Yung-Chun LI, Huai-Mu WANG, Chien-Chung HO, Yuan-Hao CHANG, Tei-Wei KUO
  • Patent number: 11664058
    Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: May 30, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Wen Hu, Yung-Chun Li