Patents by Inventor YUNG CHUN LI
YUNG CHUN LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11010244Abstract: A memory data management method includes the following steps reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to increase a first threshold voltage of a first state data of the data for exceeding a first threshold, to increase a second threshold voltage of a second state data of the data for exceeding a second threshold, and to increase a third threshold voltage of a third state data of the data for exceeding a third threshold.Type: GrantFiled: September 16, 2019Date of Patent: May 18, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yung-Chun Li, Ping-Hsien Lin, Kun-Chi Chiang, Chien-Chung Ho
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Publication number: 20210081274Abstract: A memory data management method includes the following steps: reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to enhance a first state data of the data for exceeding a first threshold, to enhance a second state data of the data for exceeding a second threshold, and to enhance a third state data of the data for exceeding a third threshold.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Inventors: Yung-Chun LI, Ping-Hsien LIN, Kun-Chi CHIANG, Chien-Chung HO
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Patent number: 10748605Abstract: Provided is a programming method for a memory device including a memory array and a controller. The programming method including: controlling programming on a first page of a first word line by the controller; controlling programming on a first page of a second word line by the controller, the second word line being adjacent to the first word line; controlling for performing a first programming operation on a second page of the first word line by the controller; controlling programming on a first page of a third word line by the controller, the third word line being adjacent to the second word line; controlling for performing the first programming operation on a second page of the second word line by the controller; and controlling for performing a second programming operation on the second page of the first word line by the controller.Type: GrantFiled: August 8, 2018Date of Patent: August 18, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yung-Chun Li, Ping-Hsien Lin
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Publication number: 20200143899Abstract: In programming a memory device, a target memory cell is programed by a programming voltage and a programming code. First and second verification voltages are applied on the target memory cell to obtain first and second read data. Whether the target memory cell passes an actual programming verification and/or a pseudo programming verification is determined based on the programming code, the first and the second read data.Type: ApplicationFiled: January 6, 2020Publication date: May 7, 2020Inventors: Chih-Chang HSIEH, Yung-Chun LI, Ti-Wen CHEN
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Publication number: 20200051620Abstract: Provided is a programming method for a memory device including a memory array and a controller. The programming method including: controlling programming on a first page of a first word line by the controller; controlling programming on a first page of a second word line by the controller, the second word line being adjacent to the first word line; controlling for performing a first programming operation on a second page of the first word line by the controller; controlling programming on a first page of a third word line by the controller, the third word line being adjacent to the second word line; controlling for performing the first programming operation on a second page of the second word line by the controller; and controlling for performing a second programming operation on the second page of the first word line by the controller.Type: ApplicationFiled: August 8, 2018Publication date: February 13, 2020Inventors: Yung-Chun LI, Ping-Hsien LIN
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Publication number: 20190371417Abstract: In programming a memory device, a target memory cell is programmed by a programming voltage and a programming code. First and second verification voltages are applied on the target memory cell to obtain first and second read data. Whether the target memory cell passes an actual programming verification and/or a pseudo programming verification is determined based on the programming code, the first and the second read data.Type: ApplicationFiled: May 29, 2018Publication date: December 5, 2019Inventors: Chih-Chang HSIEH, Yung-Chun LI, Ti-Wen CHEN
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Patent number: 10445008Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.Type: GrantFiled: September 15, 2017Date of Patent: October 15, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yung-Chun Li, Ping-Hsien Lin, Yu-Ming Chang
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Publication number: 20190087110Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventors: Yung-Chun Li, Ping-Hsien Lin, Yu-Ming Chang
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Patent number: 9740602Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.Type: GrantFiled: July 22, 2015Date of Patent: August 22, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Ming Chang, Yung-Chun Li, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 9734912Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.Type: GrantFiled: July 12, 2016Date of Patent: August 15, 2017Assignee: Macronix International Co., Ltd.Inventors: Yung-Chun Li, Yu-Ming Chang, Ping-Hsien Lin, Hsiang-Pang Li
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Patent number: 9685233Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.Type: GrantFiled: January 13, 2014Date of Patent: June 20, 2017Assignee: Macronix International Co., Ltd.Inventors: Chih-Chang Hsieh, Ti-Wen Chen, Yung Chun Li, Kuo-Pin Chang
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Publication number: 20170148526Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.Type: ApplicationFiled: July 12, 2016Publication date: May 25, 2017Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: YUNG-CHUN LI, YU-MING CHANG, PING-HSIEN LIN, HSIANG-PANG LI
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Patent number: 9627072Abstract: A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode.Type: GrantFiled: September 17, 2015Date of Patent: April 18, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Ming Chang, Yung-Chun Li, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 9558108Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.Type: GrantFiled: September 4, 2013Date of Patent: January 31, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Ming Chang, Yung-Chun Li, Hsing-Chen Lu, Hsiang-Pang Li, Cheng-Yuan Wang, Yuan-Hao Chang, Tei-Wei Kuo
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Publication number: 20160148694Abstract: A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode.Type: ApplicationFiled: September 17, 2015Publication date: May 26, 2016Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: YU-MING CHANG, YUNG-CHUN LI, HSIANG-PANG LI, YUAN-HAO CHANG, TEI-WEI KUO
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Publication number: 20160147464Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.Type: ApplicationFiled: July 22, 2015Publication date: May 26, 2016Inventors: Yu-Ming Chang, Yung-Chun Li, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 9305638Abstract: Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.Type: GrantFiled: October 29, 2014Date of Patent: April 5, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Ming Chang, Yung-Chun Li, Chih-Chang Hsieh, Shih-Fu Huang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 9025375Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.Type: GrantFiled: October 22, 2013Date of Patent: May 5, 2015Assignee: Macronix International Co., Ltd.Inventors: Yu-Ming Chang, Yung-Chun Li, Hsing-Chen Lu, Hsiang-Pang Li, Cheng-Yuan Wang, Yuan-Hao Chang, Tei-Wei Kuo
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Publication number: 20140307505Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.Type: ApplicationFiled: October 22, 2013Publication date: October 16, 2014Applicant: Macronix International Co., LtdInventors: Yu-Ming Chang, Yung-Chun Li, Hsing-Chen Lu, Hsiang-Pang Li, Cheng-Yuan Wang, Yuan-Hao Chang, Tei-Wei Kuo
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Publication number: 20140310447Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.Type: ApplicationFiled: September 4, 2013Publication date: October 16, 2014Applicant: Macronix International Co., Ltd.Inventors: YU-MING CHANG, YUNG-CHUN LI, HSING-CHEN LU, HSIANG-PANG LI, CHENG-YUAN WANG, YUAN-HAO CHANG, TEI-WEI KUO