Abstract: Provided are a wireless power apparatus, a charging dock and an electronic equipment. In the wireless power apparatus, a housing is provided with a mounting cavity; a first battery is disposed within the mounting cavity; multiple first magnetic pieces are disposed in the housing and are configured for adsorbing multiple first adsorption pieces of an equipment body, respectively; a first charging assembly is configured to charge the first battery, a wireless power supply assembly is disposed within the mounting cavity, is electrically connected to the first battery, and is capable of transmitting power of the first battery to the equipment body.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: Provided is a method for preventing or treating a liver disease, including administering a therapeutically effective amount of pharmaceutical composition to a subject in need, and the pharmaceutical composition includes the isothiocyanate structural modified compound and a pharmaceutically acceptable carrier thereof.

Abstract: An artificial bone plate unit and an assembleable artificial bone plate are provided. The artificial bone plate unit includes a plate body, multiple connecting pins, connecting holes, drug cavities, and drug-releasing openings. The plate body has two main surfaces and a peripheral surface connected between the two main surfaces. The connecting pins and the connecting holes are formed on the plate body and arranged along the peripheral surface on the plate body. The connecting holes correspond in shape to the connecting pins. The drug cavities are formed in the artificial bone plate unit and are connected to the drug-releasing openings. The artificial bone plate units are connected using the connecting pins and the connecting holes to form the assembleable artificial bone plate. The assembleable artificial bone plate can be bent into the shape of a defect area of the skull, which saves material and time.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Abstract: A method of making a semiconductor device includes forming a circuit layer over a substrate. The method further includes depositing an insulator over the substrate. The method further includes patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench is on a portion of the substrate exposed by the circuit layer. The method further includes filling the test line trench to define a test line electrically connected to the circuit layer. The method further includes filling the first trench and the second trench to define a capacitor.

Abstract: A headphone includes a headgear and two earmuffs connected to opposite ends of the headgear, and each of the earmuffs includes an adjustment assembly. The adjustment assembly includes a base, two elastic members, two protrusions, and two sliding blocks. The base has two opposite accommodating parts and two guiding grooves. The elastic members are disposed in the accommodating parts, respectively, and the elastic members extend along a first axial direction. The protrusions are slidably connected to the guiding grooves, respectively, and protrude into the accommodating parts. The sliding blocks are disposed in the accommodating parts, respectively, and each of the sliding blocks is respectively connected between the corresponding protrusion and the corresponding elastic member.

Abstract: A layout of signal traces includes a first set of signal traces and a second set of signal traces that are used for transmitting a first differential signal and a second differential signal respectively. Each set of signal traces includes a first part, a second part, and a third part along the direction of signal transmission. Different parts of the same signal trace as a whole is not straight. All the first parts are in a first signal layer and parallel. The second parts of the two sets of signal traces are in a second signal layer and the first signal layer, respectively, and are across each other. The second part of the first/second set of signal traces is coupled with the first and third parts of the first/second set of signal traces. All the third parts are in the first signal layer and parallel.

Abstract: A shielding circuit applied to a semiconductor device includes a first shielding structure and a second shielding structure. The first shielding structure forms a first closed loop and is disposed adjacent to an inductor comprised in the semiconductor device. The second shielding structure forms a second closed loop and is disposed adjacent to an electronic component coupled to the inductor.

Abstract: A dental preparation block guide comprises a chamber that is customized to receive at least one tooth of a patient for a shape-optimized restoration of the at least one tooth; and a channel formed in a surface of the block guide at a location selected relative to the shape-optimized restoration to be performed, the channel comprising an aperture extending through the surface to the chamber such that a dental handpiece can be inserted into and guided within the channel while a tool of the dental handpiece can interact with the at least one tooth in the chamber through the aperture to form a shape-optimized preparation in the at least one tooth to receive the shape-optimized restoration. Related methods and system, as well as other devices, also are disclosed.

Abstract: A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region comprises a well layer and a barrier layer, wherein the barrier layer has a band gap; a first electron blocking layer between the second semiconductor structure and the active region, wherein the first electron blocking layer comprises a band gap which is greater than the band gap of the barrier layer; a first aluminum-containing layer between the first electron blocking layer and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; a confinement layer between the first aluminum-containing layer and the active region; and a second aluminum-containing layer between the second semiconductor structure and the first electron blocking layer; wherein both the first alumi

Abstract: Aspects of the disclosure relate to a local oscillator frequency divider for a receiver or transmitter. In this regard a frequency divider has a first frequency input coupled to a first oscillator frequency output, a second frequency input coupled to a complementary second oscillator frequency output, a first in-phase/quadrature (I/Q) divided frequency output, and a complementary second I/Q divided frequency output. The frequency divider further has a first alternating current (AC) coupling capacitor between the first frequency input and the first oscillator frequency output and a second AC coupling capacitor between the second frequency input and the second oscillator frequency output.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Abstract: A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region includes multiple alternating well layers and barrier layers, wherein each of the barrier layers has a band gap, the active region further includes an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region, wherein the electron blocking region includes a band gap, and the band gap of the electron blocking region is greater than the band gap of one of the barrier layers; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the electron blocking region; a confinement layer between the fi

Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region comprises multiple alternating well layers and first barrier layers, wherein each of the first barrier layers has a band gap, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; a first electron blocking layer between the second semiconductor structure and the active region, wherein the first electron blocking layer having a band gap greater than the band gap of one of the first barrier layers; a first aluminum-containing layer between the first electron blocking layer and the active region, wherein the first aluminum-containing layer has a first thickness and a band gap greater than the band gap of the first electron blocking layer; and a second aluminum-conta

Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.

Abstract: Aspects of the disclosure relate to a local oscillator frequency divider for a receiver or transmitter. In this regard a frequency divider has a first frequency input coupled to a first oscillator frequency output, a second frequency input coupled to a complementary second oscillator frequency output, a first in-phase/quadrature (I/Q) divided frequency output, and a complementary second I/Q divided frequency output. The frequency divider further has a first alternating current (AC) coupling capacitor between the first frequency input and the first oscillator frequency output and a second AC coupling capacitor between the second frequency input and the second oscillator frequency output.

Abstract: A transceiver interface circuit, comprising a driver amplifier (DA), a load line impedance modulation circuit coupled to the DA; and multiple selectable output ports coupled to the load line impedance modulation circuit, an impedance presented by the load line impedance modulation circuit being adjustable dependent on at least a number of output ports coupled to the load line impedance modulation circuit.

Abstract: A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.