Abstract: A purification device for exercise environment is provided and includes a main body, a purification unit, a gas guider and a gas detection module. The purification unit, the gas guider and the gas detection module are disposed in the main body to guide the gas outside the main body through the purification unit for filtering and purifying the gas, and discharge a purified gas. The gas detection module detects particle concentration of suspended particles contained in the purified gas. The gas guider is controlled to operate and export the gas at an airflow rate within 3 minutes. The particle concentration of the suspended particles contained in the purified gas, which is filtered by the purification unit, is reduced to and less than 0.75 ?g/m3. Consequently, the purified gas is filtered, and an exerciser in an exercise environment can breathe with safety.

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

Abstract: A projector and a control method are provided. The projector includes a control unit, a storage medium, and a projection module. The control unit includes a script interpreter. The control method includes: detecting whether a first script is stored in the storage medium by the control unit when the projector is in an operation state, in which the first script includes a first script language instruction; interpreting the first script through the script interpreter so as to obtain the first script language instruction in response to the first script being stored in the storage medium; and configuring a display parameter of the projection module according to the first script language instruction, in which the projection module plays a multimedia file according to the display parameter.

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.

Abstract: A three dimension memory device, such as a three dimensional AND flash memory is provided. The three dimension memory device includes a plurality of memory arrays, a plurality of bit line switches, and a plurality of source line switches. The memory array has a plurality of memory cell rows respectively coupled to a plurality of source lines and bit lines. The bit line switches and the source line switches are respectively implemented by a plurality of first transistors and second transistors. The first transistors are coupled to a common bit line and the bit line. The second transistors are coupled to a common source line and the source lines. The first transistors are P-type transistors or an N-type transistors with a triple-well substrate, and the second transistors are P-type transistor or an N-type transistors with a triple-well substrate.

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.

Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.

Abstract: The present invention relates to a method and a pharmaceutical composition for treating an HCC negative for HBV/HCV, comprising administering a subject in need thereof an therapeutically effective amount of an inhibitory agent to control the genetic alteration of lipid homeostasis associated genes, including CD36 amplification and ABCG4 deletion. According to the present invention, medicines targeting the lipid metabolism pathways are developed to treat HCC patients with CD36 amplification and/or ABCG4 deletion.