Abstract: A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period.

Abstract: A sense amplifying method, applied in a memory having a memory cell and a reference cell, includes: charging the memory cell and the reference cell to have a cell current and a reference current, respectively; duplicating the cell current and the reference current to respectively generate a mirrored cell current via a first current path and a mirrored reference current via a second current path and equalizing a first voltage drop generated as the mirrored cell current flows by the first current path and a second voltage drop generated as the mirrored reference current flows by the second current path; and removing the equalization of the first voltage drop and the second voltage drop and adjusting first voltage drop and the second voltage drop according to a first current flowing by the first current path and a second current flowing by the second current path.

Abstract: A decoding circuit for decoding a command is provided. The received command is transmitted during at least two clock periods of a clock signal, and the received command is divided to a former encoded data and a latter encoded data. The decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command.

Abstract: A method for programming a MLC memory includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL?K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.

Abstract: An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage.

Abstract: A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated.

Abstract: A fixture component for a liquid crystal display (LCD) module (LCD) is provided. The fixture component clamps and encloses the LCD module with a front cover and an enclosing member to clamp and wrap the LCD module, so as to form an LCD assembly. A visible portion is formed on a front side surface of the front cover in a protrusive manner, corresponding to a display side of the LCD module. The visible portion enhances the antistatic property of the LCD module. Meanwhile, the visible portion fits an opening of a case, so that the LCD assembly is mounted and fixed in the case more easily.

Abstract: An illumination button applied to an illumination switch assembly is provided. The illumination button includes a light guide body and a button cap. The light guide body is disposed in the button cap to press a switch element with a pressing bump and to receive light from a light source with a light receiving structure. The light received by the light receiving structure is guided by the light guide body to leave a top surface of the button cap through a light exiting structure. Two connecting members are disposed on an edge the button cap, wherein the two connecting members provided to be clamped by clamping members disposed on an inner surface of a housing, so as to hold the button cap in a button hole of the housing. Therefore, the button cap is able to be installed to the housing quickly with out using a tool.

Abstract: A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period.

Abstract: A closure device includes: a main body having first and second shoulders; a door secured rotatably to the main body and having first and second door edges; an engaging member; an engaging mechanism; and a second pivot axle. The first shoulder and the first door edge respectively have a through hole and a first axle hole. The engaging member and the engaging mechanism are disposed respectively at an inner side of the main body. The engaging member includes a first pivot axle extending through the through hole and the first axle hole, and a positioning piece extending radially from the first pivot axle and engaging the engaging mechanism. One of the second shoulder and the second door edge has a second axle hole, while the other of the second shoulder and the second door edge has the second pivot axle extending through the second axle hole.

Abstract: A key mechanism for actuating a circuit board includes a housing whereon an opening is formed, a key button installed inside the opening of the housing, and a waterproof structure installed between the key button and the circuit board for preventing fluid from leaking into the circuit board via an interface of the housing and the key button. A space is formed between the waterproof structure and the key button for containing the fluid leaking from the interface of the housing and the key button. The space is lower than the interface of the housing and the key button.

Abstract: A static latch includes a clock-based driver, an actuation circuit, and a weak latched unit. The clock-based driver includes first node, second node, a driving unit, first pass switch, and second pass switch. The driving unit drives the first node corresponding to first voltage in response to first level of an input signal and drives the second node having second voltage in response to second level of the input signal. The first pass switch drives an output node having a latched signal corresponding to the first voltage in response to the clock signal. The second pass switch drives the output node corresponding to the second voltage in response to the inverted clock signal. The actuation circuit drives the output node corresponding to the second voltage in response to the clock signal. The weak latch unit keeps the level of the latched signal when the static latch is disabled.

Abstract: A method adjusts driving ability of an output buffer. The output buffer has multiple driving ability classes. The method includes the following steps. First, the driving ability of the output buffer is initialized as an initial class among the driving ability classes. Next, a voltage at an output terminal of the output buffer is initialized to an initial voltage. Then, an input voltage is inputted via the input terminal at a first time instant. Next, an output voltage outputted from the output terminal is sampled to obtain a voltage value at a second time instant. Then, whether the voltage value satisfies a predetermined condition is judged. Next, if the voltage value satisfies the predetermined condition, the driving ability class of the output buffer is recorded and set.

Abstract: An electronic device includes a base and a display screen. The base includes an upper surface and a plurality of spaced-apart positioning members disposed on the upper surface. The display screen includes a screen body, and a support member connected pivotably to a rear face of the screen body and rotatable relative to the screen body. The support member has one end connected to the screen body, and an opposite end engageable with a selected one of the positioning members so as to support and position the screen body stably at a selected angular position.

Abstract: A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated.

Abstract: A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage.

Abstract: A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period.

Abstract: A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage.

Abstract: A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.

Abstract: A controlling output buffer slew rate method and an output buffer circuit for a memory device is provided. The output buffer include an output stage formed by a PMOS transistor and a NMOS transistor electrically connected in series, a pre-driver for respectively controlling each gate terminal of the PMOS transistor and the NMOS transistor in order to bring these transistors to the turning-on threshold, a first wire, for transmitting a pull-up signal, coupled between the output stage and the pre-driver, and a second wire, for transmitting a pull-down signal, coupled between the output stage and the pre-driver. After a DATA signal transition (logic state is changed from “H” to “L” or “L” from to “H”), the PMOS or NMOS transistor is turned off first, and then the NMOS or PMOS transistor is turned on due to the time difference between the pull-up signal and the pull-down signal.