Patents by Inventor Yung-Hao Lin

Yung-Hao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240173370
    Abstract: Provided herein are hydrogels that include a plurality of bacteriophages located within and covalently bonded to the hydrogel interior. The hydrogel is engineered to facilitate a controlled sustained release of the connected bacteriophages, e.g., to or within the body of a patient suffering from a bacterial infection. Also provided are methods for forming the provided hydrogels, and for using the hydrogels to treat a patient suffering from a bacterial infection.
    Type: Application
    Filed: March 25, 2022
    Publication date: May 30, 2024
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ovijit CHAUDHURI, Paul L. BOLLYKY, Robert MANASHEROB, Yung-Hao LIN, Derek AMANATULLAH
  • Patent number: 11955542
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: April 9, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Patent number: 11664430
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: May 30, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih Lin, Chang-Xiang Hung, Chia-Ching Huang, Yung-Hao Lin, Chia-Hao Lee
  • Publication number: 20210257466
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Chang-Xiang HUNG, Chia-Ching HUANG, Yung-Hao LIN, Chia-Hao LEE
  • Publication number: 20210226048
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 22, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Shin-Cheng LIN, Yung-Hao LIN
  • Patent number: 11043563
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 22, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih Lin, Chang-Xiang Hung, Chia-Ching Huang, Yung-Hao Lin, Chia-Hao Lee
  • Patent number: 10998434
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 4, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Patent number: 10867993
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 15, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Fu-Hsin Chen, Shin-Cheng Lin, Yung-Hao Lin, Hsin-Chih Lin
  • Publication number: 20200219870
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Fu-Hsin CHEN, Shin-Cheng LIN, Yung-Hao LIN, Hsin-Chih LIN
  • Patent number: 10692857
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 23, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Fu-Hsin Chen, Shin-Cheng Lin, Yung-Hao Lin, Hsin-Chih Lin
  • Patent number: 10629475
    Abstract: A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Patent number: 10483362
    Abstract: A HEMT device is provided. The HEMT device includes a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, a drain, a trench, and a metal layer. The buffer layer is formed on the substrate. The first epitaxial layer is formed on the buffer layer. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is disposed in the insulating layer. The source and the drain are disposed in the insulating layer. The trench passes through the insulating layer and the second epitaxial layer, and extends into the first epitaxial layer. The metal layer is formed on the insulating layer to connect to the source, and is filled into the trench to electrically connect to the first epitaxial layer and the source.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: November 19, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Publication number: 20190348411
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Fu-Hsin CHEN, Shin-Cheng LIN, Yung-Hao LIN, Hsin-Chih LIN
  • Patent number: 10424659
    Abstract: A high electron mobility transistor includes a buffer layer, a threshold voltage adjustment layer, a band adjustment layer, a first enhancement layer, a gate electrode, and source/drain electrodes. The threshold voltage adjustment layer is disposed on the buffer layer. A channel region is disposed in the buffer layer adjacent to an interface between the buffer layer and the threshold voltage adjustment layer. The band adjustment layer is disposed on the threshold voltage adjustment layer. The first enhancement layer is conformally covering the threshold voltage adjustment layer and the band adjustment layer. The gate electrode is disposed on the first enhancement layer. The source/drain electrodes are disposed on the buffer layer through the threshold voltage adjustment layer and the first enhancement layer on opposite sides of the gate electrode respectively. The threshold voltage adjustment layer and the first enhancement layer are III-V semiconductors.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 24, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Hsin-Chih Lin, Yung-Hao Lin, Chia-Ching Huang
  • Publication number: 20190280092
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 12, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Chang-Xiang HUNG, Chia-Ching HUANG, Yung-Hao LIN, Chia-Hao LEE
  • Publication number: 20190252505
    Abstract: A HEMT device is provided. The HEMT device includes a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, a drain, a trench, and a metal layer. The buffer layer is formed on the substrate. The first epitaxial layer is formed on the buffer layer. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is disposed in the insulating layer. The source and the drain are disposed in the insulating layer. The trench passes through the insulating layer and the second epitaxial layer, and extends into the first epitaxial layer. The metal layer is formed on the insulating layer to connect to the source, and is filled into the trench to electrically connect to the first epitaxial layer and the source.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Shin-Cheng LIN, Yung-Hao LIN
  • Patent number: 10355096
    Abstract: A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 16, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Publication number: 20190198654
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Shin-Cheng LIN, Yung-Hao LIN
  • Publication number: 20190198384
    Abstract: A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Shin-Cheng LIN, Yung-Hao LIN
  • Patent number: 10325990
    Abstract: A HEMT device is provided. The HEMT device includes a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, a drain, a trench, and a metal layer. The buffer layer is formed on the substrate. The first epitaxial layer is formed on the buffer layer. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is disposed in the insulating layer. The source and the drain are disposed in the insulating layer. The trench passes through the insulating layer and the second epitaxial layer, and extends into the first epitaxial layer. The metal layer is formed on the insulating layer to connect to the source, and is filled into the trench to electrically connect to the first epitaxial layer and the source.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 18, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin