Abstract: A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.

Abstract: A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.

Abstract: A HEMT device is provided. The HEMT device includes a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, a drain, a trench, and a metal layer. The buffer layer is formed on the substrate. The first epitaxial layer is formed on the buffer layer. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is disposed in the insulating layer. The source and the drain are disposed in the insulating layer. The trench passes through the insulating layer and the second epitaxial layer, and extends into the first epitaxial layer. The metal layer is formed on the insulating layer to connect to the source, and is filled into the trench to electrically connect to the first epitaxial layer and the source.

Abstract: A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.

Abstract: A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.

Abstract: A HEMT device is provided. The HEMT device includes a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, a drain, a trench, and a metal layer. The buffer layer is formed on the substrate. The first epitaxial layer is formed on the buffer layer. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is disposed in the insulating layer. The source and the drain are disposed in the insulating layer. The trench passes through the insulating layer and the second epitaxial layer, and extends into the first epitaxial layer. The metal layer is formed on the insulating layer to connect to the source, and is filled into the trench to electrically connect to the first epitaxial layer and the source.

Abstract: A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.

Abstract: A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.

Abstract: A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.

Abstract: The embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first III-V compound layer disposed over a substrate and a second III-V compound layer disposed over the first III-V compound layer, wherein a first carrier channel is formed in the interface between the first III-V compound layer and the second III-V compound layer. The semiconductor device also includes a third III-V compound layer disposed over the second III-V compound layer and a fourth III-V compound layer disposed over the third III-V compound layer, wherein a second carrier channel is formed in an interface between the third III-V compound layer and the fourth III-V compound layer. The semiconductor device includes a gate structure and S/D regions disposed on two opposite sides of the gate structure, wherein the first carrier channel and the second carrier channel are extended between the S/D regions.

Abstract: Embodiments of the disclosure relate to an enhanced-mode high electron mobility transistor. The enhanced-mode high electron mobility transistor includes a substrate, a first III-V semiconductor layer disposed on the substrate, a second III-V semiconductor layer disposed on the first III-V semiconductor layer, a third III-V semiconductor layer disposed on the second III-V semiconductor layer, an amorphous region extending from the third III-V semiconductor layer into the second III-V semiconductor layer and the first III-V semiconductor layer to serve as an isolation region, and a gate electrode disposed in the amorphous region. The second III-V semiconductor layer and the third III-V semiconductor layer include different materials to form a heterojunction.

Abstract: A semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, wherein the first gallium nitride layer has a first conductivity type. The semiconductor device also includes a second gallium nitride layer disposed on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductivity type, and the first gallium nitride layer has a dopant concentration which is greater than that of the second gallium nitride layer. The semiconductor device further includes an anode electrode disposed on the second gallium nitride layer, a cathode electrode disposed on and in direct contact with the first gallium nitride layer, and an insulating region disposed on and in direct contact with the first gallium nitride layer, wherein the insulating region is located between the cathode electrode and the second gallium nitride layer.

Abstract: A high electron mobility transistor includes a buffer layer disposed on a substrate. A barrier layer is disposed on the buffer layer. A channel layer is disposed in the buffer layer and is adjacent to the interface between the buffer layer and the barrier layer. A gate electrode is disposed on the barrier layer. A drain electrode is disposed on the barrier layer on a first side of the gate electrode. A source electrode is disposed on the barrier layer on a second side of the gate electrode. A first enhancement layer is disposed on the barrier layer and the channel layer between the gate electrode and the drain electrode and is not in direct contact with the gate electrode, the source electrode, or the drain electrode. The first enhancement layer is an N-type doped III-V semiconductor.

Abstract: A super high voltage device includes a first gate, a second gate, a drain, a first source, a second source, and a third source. The first gate is used for receiving a first control signal generated from a pulse width modulation controller. The second gate is used for receiving a second control signal generated from the pulse width modulation controller. The drain is used for receiving an input voltage. First current flowing from the drain to the first source varies with the first control signal and the input voltage. The second control signal is used for controlling turning-on and turning-off of second current flowing from the drain to the second source and third current flowing from the drain to the third source. The third source is proportional to the second current.

Abstract: A super high voltage device includes a first gate, a second gate, a drain, a first source, a second source, and a third source. The first gate is used for receiving a first control signal generated from a pulse width modulation controller. The second gate is used for receiving a second control signal generated from the pulse width modulation controller. The drain is used for receiving an input voltage. First current flowing from the drain to the first source varies with the first control signal and the input voltage. The second control signal is used for controlling turning-on and turning-off of second current flowing from the drain to the second source and third current flowing from the drain to the third source. The third source is proportional to the second current.

Abstract: An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

Abstract: An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.

Abstract: An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

Abstract: An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.