Abstract: A semiconductor device includes a substrate and a bump pattern of a plurality of bumps on the substrate. The bump pattern includes a plurality of rows and a plurality of columns. Bumps of the plurality of bumps include one or more radio frequency (RF) signal bumps for transmission of RF signals during operation or probing of the semiconductor device. Each RF signal bump of the one or more RF signal bumps is surrounded by at least three neighboring bumps immediately adjacent the RF signal bump. Each neighboring bump is selected from the group consisting of (i) a ground bump configured to receive a ground voltage during the operation or probing of the semiconductor device, and (ii) another RF signal bump which defines, together with said RF signal bump, a pair of differential signal bumps for transmission of differential RF signals during the operation or probing of the semiconductor device.

Abstract: Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region.

Abstract: In some embodiments, a probe card includes a PCB, a substrate, a pair of probes, a capacitive device and a first part. The PCB includes a pair of conductive paths through a first surface and a second surface of the PCB. The substrate includes a pair of conductive paths through a first surface and a second surface of the substrate. The conductive paths of the substrate and the corresponding conductive paths of the PCB are coupled between the first surface of the substrate and the second surface of the PCB. The probes and the corresponding conductive paths of the substrate are coupled beyond the second surface of the substrate. The capacitive device is coupled between a first conductive path and a second conductive path through the PCB, the substrate and the probes. The first part is configured beyond the second surface of the PCB, and holds the capacitive device.

Abstract: A semiconductor device includes a substrate and a bump pattern of a plurality of bumps on the substrate. The bump pattern includes a plurality of rows and a plurality of columns. Bumps of the plurality of bumps include one or more radio frequency (RF) signal bumps for transmission of RF signals during operation or probing of the semiconductor device. Each RF signal bump of the one or more RF signal bumps is surrounded by at least three neighboring bumps immediately adjacent the RF signal bump. Each neighboring bump is selected from the group consisting of (i) a ground bump configured to receive a ground voltage during the operation or probing of the semiconductor device, and (ii) another RF signal bump which defines, together with said RF signal bump, a pair of differential signal bumps for transmission of differential RF signals during the operation or probing of the semiconductor device.

Abstract: In a method of improving bump allocation for a semiconductor device and a semiconductor device with improved bump allocation, a predetermined signal bump is surrounded with at least three bumps, each being a ground bump or a paired differential signal bump.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.

Abstract: Among other things, one or more techniques and/or systems are provided for shielding a signal pin. A signal pin, such as a signal pin within a probe card used to test electronic devices, such as integrated circuits, is shielded from interference signals, which are emitted from other signal pins within the probe card. Shielding the signal pin mitigates cross-talk issues and/or impendence control issues associated with signals that are carried by the signal pin. In one example, one or more shield pins are arranged with respect to the signal pin according to a shield configuration. For example, the shield configuration comprises a plane of signal pins, a substantially regular layout of signal pins, or a polygonal layout of signal pins, etc. In this way, one or more shield pins inhibit unintended interactions or effects that otherwise occur among two or more signal pins.

Abstract: A probe card for wafer level test includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes a first surface having a first pitch and a second surface having a second pitch substantially less than the first pitch, a printed circuit board configured approximate the first surface of the space transformer, a first power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line to the printed circuit board, and a second power plane disposed on a surface of the printed circuit board and patterned to couple the power line and the ground line of the space transformer to the printed circuit board, wherein the second power plane is in electrical connection with the first power plane.

Abstract: In some embodiments, a probe card includes a PCB, a substrate, a pair of probes, a capacitive device and a first part. The PCB includes a pair of conductive paths through a first surface and a second surface of the PCB. The substrate includes a pair of conductive paths through a first surface and a second surface of the substrate. The conductive paths of the substrate and the corresponding conductive paths of the PCB are coupled between the first surface of the substrate and the second surface of the PCB. The probes and the corresponding conductive paths of the substrate are coupled beyond the second surface of the substrate. The capacitive device is coupled between a first conductive path and a second conductive path through the PCB, the substrate and the probes. The first part is configured beyond the second surface of the PCB, and holds the capacitive device.

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes an inductive or capacitive wireless communication structure located on a die region of the integrated circuit. This wireless communication structure is configured to wirelessly receive a test stimulus vector to test circuitry on the die region. The integrated circuit also includes a landing region having a size and location suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact with the landing region. The landing region provides a DC power supply to the circuitry on the die region while the test stimulus vector is wirelessly received.

Abstract: A probe card for wafer level test includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes a first surface having a first pitch and a second surface having a second pitch substantially less than the first pitch, a printed circuit board configured approximate the first surface of the space transformer, a first power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line to the printed circuit board, and a second power plane disposed on a surface of the printed circuit board and patterned to couple the power line and the ground line of the space transformer to the printed circuit board, wherein the second power plane is in electrical connection with the first power plane.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.

Abstract: The present disclosure provides a probe card for wafer level testing. The probe card includes a space transformer having first power/ground lines and first signal lines embedded therein, wherein the first power/ground and signal lines are configured to have a first wiring pitch on a first surface and a second wiring pitch on a second surface, the second wiring pitch being substantially less than the first wiring pitch; a printed circuit board bonded to the first surface of the space transformer, wherein the printed circuit board includes second power/ground lines and second signal lines embedded in the printed circuit board and coupled to the first power/ground and signal lines; and conductive lines configured to a surface of the printed circuit board remote to the first surface of the space transformer, wherein each of the conductive lines includes a first end coupled to one of the second signal lines and a second end coupled to a different location of the printed circuit board.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.

Abstract: An assembly includes a lower guide plate having a first plurality of through-holes therein, and an upper guide plate over the lower guide plate. The upper guide plate includes a second plurality of through-holes therein. The assembly further includes a plurality of probe pins. Each of the probe pins is inserted through one of the first plurality of through-holes and one of the second plurality of through-holes. The assembly further includes a plurality of probe pin stoppers, each attached to one of the probe pins, wherein the plurality of probe pin stoppers has lateral sizes greater than lateral sizes of the second plurality of through-holes. The plurality of probe pin stoppers is located over the upper guide plate.

Abstract: In accordance with an embodiment, a probe card structure comprises a base board, a connection interposer over the base board, a substrate over the connection interposer, and a fixture over the substrate securing the substrate and the connection interposer to the base board. The connection interposer comprises interposer electrodes that provide an electrical connection between electrodes on the base board and first electrodes on the substrate.

Abstract: Among other things, one or more techniques and/or systems are provided for shielding a signal pin. A signal pin, such as a signal pin within a probe card used to test electronic devices, such as integrated circuits, is shielded from interference signals, which are emitted from other signal pins within the probe card. Shielding the signal pin mitigates cross-talk issues and/or impendence control issues associated with signals that are carried by the signal pin. In one example, one or more shield pins are arranged with respect to the signal pin according to a shield configuration. For example, the shield configuration comprises a plane of signal pins, a substantially regular layout of signal pins, or a polygonal layout of signal pins, etc. In this way, one or more shield pins inhibit unintended interactions or effects that otherwise occur among two or more signal pins.

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes an inductive or capacitive wireless communication structure located on a die region of the integrated circuit. This wireless communication structure is configured to wirelessly receive a test stimulus vector to test circuitry on the die region. The integrated circuit also includes a landing region having a size and location suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact with the landing region. The landing region provides a DC power supply to the circuitry on the die region while the test stimulus vector is wirelessly received.

Abstract: In a method of improving bump allocation for a semiconductor device and a semiconductor device with improved bump allocation, a predetermined signal bump is surrounded with at least three bumps, each being a ground bump or a paired differential signal bump.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process.