Patents by Inventor Yung-jun Kim
Yung-jun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949881Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.Type: GrantFiled: April 1, 2021Date of Patent: April 2, 2024Assignees: Electronics and Telecommunications Research Institute, Kwangwoon University Research Institute for Industry Cooperation, Industry-Academia Cooperation Group of Sejong UniversityInventors: Se-Yoon Jeong, Hae-Chul Choi, Jeong-Il Seo, Seung-Kwon Beack, In-Seon Jang, Jae-Gon Kim, Kyung-Ae Moon, Dae-Young Jang, Jin-Woo Hong, Jin-Woong Kim, Yung-Lyul Lee, Dong-Gyu Sim, Seoung-Jun Oh, Chang-Beom Ahn, Dae-Yeon Kim, Dong-Kyun Kim
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Patent number: 11930179Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.Type: GrantFiled: December 27, 2019Date of Patent: March 12, 2024Assignees: Electronics and Telecommunications Research Institute, INDUSTRY ACADEMY COOPERATION FOUNDATION OF SEJONG UNI, CHIPS & MEDIA, INC, INDUSTRY-UNIVERSITY COOPERATION FOUNDATION KOREA AEROSPACE UNIVERSITYInventors: Sung Chang Lim, Jung Won Kang, Ha Hyun Lee, Jin Ho Lee, Hui Yong Kim, Yung Lyul Lee, Ji Yeon Jung, Nam Uk Kim, Myung Jun Kim, Yang Woo Kim, Dae Yeon Kim, Jae Gon Kim, Do Hyeon Park
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Patent number: 11145675Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.Type: GrantFiled: May 15, 2020Date of Patent: October 12, 2021Assignee: SK hynix Inc.Inventors: Yung Jun Kim, Won Hyo Cha, Byung Soo Park, Sang Tae Ahn, Sung Jae Chung
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Publication number: 20200279865Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Applicant: SK hynix Inc.Inventors: Yung Jun KIM, Won Hyo CHA, Byung Soo PARK, Sang Tae AHN, Sung Jae CHUNG
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Patent number: 10692885Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.Type: GrantFiled: October 25, 2018Date of Patent: June 23, 2020Assignee: SK hynix Inc.Inventors: Yung Jun Kim, Won Hyo Cha, Byung Soo Park, Sang Tae Ahn, Sung Jae Chung
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Patent number: 10525566Abstract: A chemical mechanical polishing (CMP) method includes preparing a polishing pad, determining a first load to be applied to a conditioning disk during conditioning of the polishing pad and a first indentation depth at which tips of the conditioning disk are inserted into the polishing pad when the first load is applied to the conditioning disk, preparing a conditioning disk, and positioning the conditioning disk on the polishing pad and conditioning a surface of the polishing pad by using the conditioning disk while applying the first load to the conditioning disk.Type: GrantFiled: May 23, 2017Date of Patent: January 7, 2020Assignees: SAMSUNG ELECTRONICS CO., LTD., EHWA Diamond Industrial Co., Ltd.Inventors: Myung-ki Hong, Yung-jun Kim, Sung-oh Park, Hyo-san Lee, Joo-han Lee, Kyu-min Oh, Sun-gyu Park, Seh-kwang Lee, Chan-ki Yang
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Patent number: 10483281Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.Type: GrantFiled: November 13, 2018Date of Patent: November 19, 2019Assignee: SK hynix Inc.Inventors: Yung Jun Kim, Suk Goo Kim
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Patent number: 10483203Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include channel layers protruding away from a substrate. The semiconductor memory device may include a plurality of pads respectively coupled to the channel layers. The widths of the pads may or may not be increased depending on a bending of the channel layers.Type: GrantFiled: June 30, 2017Date of Patent: November 19, 2019Assignee: SK hynix Inc.Inventor: Yung Jun Kim
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Publication number: 20190287999Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.Type: ApplicationFiled: October 25, 2018Publication date: September 19, 2019Applicant: SK hynix Inc.Inventors: Yung Jun KIM, Won Hyo CHA, Byung Soo PARK, Sang Tae AHN, Sung Jae CHUNG
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Publication number: 20190091833Abstract: A chemical mechanical polishing method includes providing a pad conditioner, such that the pad conditioner includes a base and a plurality of tips protruding from a surface of the base, adjusting a surface roughness of an upper surface of each tip of the plurality of tips, and adjusting a polishing rate of chemical mechanical polishing using the adjusted surface roughness of the upper surfaces of the plurality of tips.Type: ApplicationFiled: April 19, 2018Publication date: March 28, 2019Applicant: EHWA DIAMOND IND. CO., LTD.Inventors: Sol HAN, Yung Jun KIM, Ho Young KIM, Doo Sik MOON, Sung Oh PARK, Young Seok JANG, Sun Gyu PARK, Kyu Min OH, Joo Han LEE
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Publication number: 20190081073Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Inventors: Yung Jun KIM, Suk Goo KIM
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Patent number: 10163927Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.Type: GrantFiled: June 28, 2017Date of Patent: December 25, 2018Assignee: SK Hynix Inc.Inventors: Yung Jun Kim, Suk Goo Kim
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Publication number: 20180130737Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include channel layers protruding away from a substrate. The semiconductor memory device may include a plurality of pads respectively coupled to the channel layers. The widths of the pads may or may not be increased depending on a bending of the channel layers.Type: ApplicationFiled: June 30, 2017Publication date: May 10, 2018Applicant: SK hynix Inc.Inventor: Yung Jun KIM
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Publication number: 20180130818Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.Type: ApplicationFiled: June 28, 2017Publication date: May 10, 2018Inventors: Yung Jun KIM, Suk Goo KIM
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Publication number: 20180104792Abstract: A chemical mechanical polishing (CMP) method includes preparing a polishing pad, determining a first load to be applied to a conditioning disk during conditioning of the polishing pad and a first indentation depth at which tips of the conditioning disk are inserted into the polishing pad when the first load is applied to the conditioning disk, preparing a conditioning disk, and positioning the conditioning disk on the polishing pad and conditioning a surface of the polishing pad by using the conditioning disk while applying the first load to the conditioning disk.Type: ApplicationFiled: May 23, 2017Publication date: April 19, 2018Applicant: EHWA Diamond Industrial Co., Ltd.Inventors: Myung-ki HONG, Yung-jun KIM, Sung-oh PARK, Hyo-san LEE, Joo-han LEE, Kyu-min Oh, Sun-gyu PARK, Seh-kwang LEE, Chan-ki YANG
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Publication number: 20160305817Abstract: The present invention relates to a proximity luminance sensor obtained by assembling a housing array to a printed circuit board array using an adhesive layer, prior to separation into individual proximity luminance sensors, thereby preventing contamination or damage to lenses, decreasing the optical interference phenomenon, reducing the manufacturing cost and manufacturing time, and thus substantially improving productivity.Type: ApplicationFiled: March 5, 2014Publication date: October 20, 2016Inventors: Yung Jun KIM, Ja Guen GU, Su Seok LEE
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Patent number: 8372198Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: GrantFiled: March 6, 2008Date of Patent: February 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Publication number: 20080149021Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Publication number: 20080152866Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Patent number: 7358126Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: GrantFiled: January 17, 2006Date of Patent: April 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae