Abstract: In a method of manufacturing a semiconductor device, a preliminary insulating layer is formed on a substrate. A photoresist pattern is formed on the preliminary insulating layer. A central portion of the preliminary insulating layer is partially etched using the photoresist pattern as an etch mask to form a preliminary insulating layer pattern including a central portion and a peripheral portion on the substrate. The peripheral portion of the photoresist pattern is higher than that of the central portion of the preliminary insulating layer pattern. The preliminary insulating layer pattern is polished to form a planarized insulating layer on the substrate.

Abstract: According to embodiments of the invention, a height of a capacitor lower electrode is increased. Portions of the lower electrode and an interlayer insulating layer are etched within the interlayer insulating layer that is formed with the lower electrode thereon, so that a trench having a double damascene structure is formed. A dielectric layer and an upper electrode are formed within the trench. Therefore, shorts between metal interconnects caused by misalignments during formation of the upper electrode are prevented and consistent capacitance values may be secured.

Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

Abstract: In a method of manufacturing a semiconductor device having a stacked structure, an amorphous silicon layer may be formed on a first single crystalline silicon layer. An amorphous state of the amorphous silicon layer may be converted into a single crystalline state to form a preliminary second single crystalline silicon layer having protrusions. The protrusions may be polished to form a second single crystalline silicon layer.

Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

Abstract: According to embodiments of the invention, a height of a capacitor lower electrode is increased. Portions of the lower electrode and an interlayer insulating layer are etched within the interlayer insulating layer that is formed with the lower electrode thereon, so that a trench having a double damascene structure is formed. A dielectric layer and an upper electrode are formed within the trench. Therefore, shorts between metal interconnects caused by misalignments during formation of the upper electrode are prevented and consistent capacitance values may be secured.

Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.